tda5235 Infineon Technologies Corporation, tda5235 Datasheet - Page 26

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tda5235

Manufacturer Part Number
tda5235
Description
Enhanced Sensitivity Double-configuration Receiver With Digital Baseband Processing
Manufacturer
Infineon Technologies Corporation
Datasheet

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When defining a Multi-Configuration system requiring different RF channels, the
correct selection of channel spacing is extremely important. A general rule is not
possible, but following must be considered:
• If an additional SAW filter is used, all channels including their tolerances have to be
inside the SAW filter bandwidth.
• The distance between channels must be high enough, that no overlapping can occur.
Strong input signals may still appear as recognizable input signal in the neighboring
channel because of the limited suppression of IF Filters. Example: a typical 330kHz IF
filter has at 10.3 MHz ( 10.7 MHz - 0.4 MHz ) only 30 dB suppression. A -70 dBm input
signal appears like a -100 dBm signal, which is inside the receiver sensitivity. In critical
cases the use of two IF filters must be considered. See also
Receiver.
2.4.5.1
The divider chain consists of a band select divider 1/2/3, an I/Q-divider by 4 which
provides an orthogonal 1st local oscillator signal for the first image reject mixer with the
necessary high accuracy and a multi-modulus divider controlled by the Sigma-Delta
Modulator. With the band select divider, the wanted frequency band is selected. Divide
by 1 selects the 915 MHz and 868 MHz band, divide by 2 selects the 434 MHz band and
divide by 3 selects the 315 MHz band. The ISM band selection is done via bit group
BANDSEL in x_PLLINTC1 register.
2.4.5.2
The 3
LSB is always high, and is clocked by the XTAL oscillator. This determines the
achievable frequency resolution.
The Automatic Frequency Control Unit filters the actual frequency offset from the FSK
demodulator data and calculates the necessary correction of the divider factor to achieve
the nominal IF center frequency.
Data Sheet
rd
order Sigma-Delta Modulator (SDM) has a 22 bit wide input word, however the
PLL Dividers
Digital Modulator
26
Chapter 2.4.3 RF/IF
Functional Description
V1.0, 2010-02-19
TDA5235

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