tda5235 Infineon Technologies Corporation, tda5235 Datasheet - Page 38

• Manufacturer Part Number: tda5235
• Description: Enhanced Sensitivity Double-configuration Receiver With Digital Baseband Processing
• Manufacturer: Infineon Technologies Corporation

2.4.8
Figure 15
The digital baseband receiver comprises a matched data filter, a clock and data
recovery, a data slicer, a line decoder, a wake-up generator, a frame synchronization
and a data FIFO. The recovered data and clock signals are accessible via 2 separate
pins. The FIFO data buffer is accessible via the SPI bus interface.
2.4.8.1
The data filter is a matched filter (MF). The frequency response of a matched filter has
ideally the same shape as the power spectral density (PSD) of the originally transmitted
signal, therefore the signal-to-noise ratio (SNR) at the output of the matched filter
becomes maximum. The input sampling rate of the baseband receiver has to be
between 8 and 16 samples per chip. The oversampling factor within this range is
depending on the data rate (see
this oversampling. After the MF a fractional sample rate converter (SRC) is applied using
linear interpolation. Depending on the data rate decimation is adjusted within the range
1...2. Finally, at the output of the fractional SRC the sampling rate is adjusted to 8
samples per chip for further processing.
To distinguish whether the incoming signal is really a signal or only noise adequate
detectors for ASK and FSK are built in.
Data Sheet
Demodulator
From ASK/
FSK
samples
per chip
8 to 16
Digital Baseband (DBB) Receiver
Data Filter and Signal Detection
Functional Block Diagram Digital Baseband Receiver
detector
(Sliced RAW Data for
external processing )
FSK
RAW Data Slicer
Matched Filter
for external
processing
adjust_length
Invert
DATA
Data
DINVEXT
for external processing )
(Matched Filtered Data
fs
DATA_MATCHFIL
fractional SRC
out
/ fs
SIGN
Invert
MUX
in
Data
= 0.5 … 1.0
Figure
bypass
SRC
10). The MF has to be adjusted accordingly to
38
Detector
Signal
CR PLL
Slicer
Slicer
Data
Chip Data
Decoder
Blind Sync
CDR PLL
Functional Description
Initial Phase & Data rate
CHIPDINV
(TSI Detector)
Invert
Chip
Data
Decoder
WU Unit
Framer
V1.0, 2010-02-19
RXSTR RXD
chip_data_clock
TDA5235
chip_data
data_clk
data
eom
fsync
wakeup
sync
CH_STR
CH_DATA
FIFO