tda5235 Infineon Technologies Corporation, tda5235 Datasheet - Page 67

• Manufacturer Part Number: tda5235
• Description: Enhanced Sensitivity Double-configuration Receiver With Digital Baseband Processing
• Manufacturer: Infineon Technologies Corporation

Figure 38
Two important system parameters are described in this section: the Synchronization
Search Time Out (SYSRCTO) and the Inter-Frame Time. The processing sequence of
a payload frame is shown in
Figure 39
The overall system latency time is calculated in two steps: T
input (ASK) / limiter output (FSK) and the CDR input, and T
Sync Found and the Framer output (decoded data available).
T
T
T
• digital frontend processing delay
• matched filter computation time
• signal detector delay
T
• Data Slicer computation time
• Framer computation time.
1) The 0.5 T have to be added in case of activation of Bi-phase mark / space decoding mode and Data Slicer Bit
Data Sheet
4
4
1
2
= 1 T. T is the nominal duration of one data bit.
mode without Code Violation (see register x_SLCCFG)
is the time between Symbol Sync Found and Chip Data output (RX mode TMCDS).
latency time include: (T
latency time include: (T
chip data available
CDR input
input data
data available
Structure of Payload Frame
Data Latency
RUNIN
T
1
symbol sync found
RUNIN
T
RUNIN
3
1
2
TSI
= 12.5µs + 2 T)
= 1.5 T + 0.5 T
Figure
T
T
4
2
TSI
39.
TSI
TSI
67
1)
)
PAYLOAD
2
1
is the time between Symbol
is the delay between ADC
T
Functional Description
RUNIN
2
PLL re-synchronization
T
2
RUNIN
RUNIN
V1.0, 2010-02-19
TDA5235