tda5235 Infineon Technologies Corporation, tda5235 Datasheet - Page 49

• Manufacturer Part Number: tda5235
• Description: Enhanced Sensitivity Double-configuration Receiver With Digital Baseband Processing
• Manufacturer: Infineon Technologies Corporation

In bit mode the data slicer has only one threshold (zero) to distinguish between the two
levels of the matched filter output. The data slicer internally maps a positive value to a 1
and a negative value to a -1. After that, the selected line decoding is applied.
Summary of data slicer modes in the TDA5235:
Data Slicer Chip mode:
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Data Slicer Bit mode:
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In Data Slicer Bit mode an even number of TSI chips needs to be used.
When Data Slicer Bit mode is selected, then the the last chip of RUNIN must be different
from first chip of TSI (e.g. Runin-bit sequence 000000 and TSI bit sequence 0xx...xxx is
OK). Otherwise the TSI will not be detected correctly.
On using Data Slicer Bit Mode, the Wake-up criteria Equal Bits Detection and Pattern
Detection cannot be applied.
A line decoder decodes the incoming data chips according to the encoding scheme (see
Chapter
Data Sheet
Code violations detectable (TSI, or EOM)
Performance loss compared to bit mode
Activation via setting register x_SLCCFG to a value of
No code violations detectable
Full performance
In case of Bi-phase mark and Bi-phase space an additional bit must be sent to ensure
correct decoding of the last bit
Activation via setting register x_SLCCFG to a value of 0x75
+ 0x90 (Chip Mode EOM-CV: For patterns with code violations in data packet and
+ 0x94 (Chip Mode EOM-Data length: For patterns with code violations in data
+ 0x95 (Chip Mode Transparent: When Framer is not used, but CH_DATA /
optimized for activated EOM code violation criterion (and optional EOM data
length criterion))
packet and optimized for activated EOM data length criterion only)
CH_STR are used for data processing)
2.4.8.2).
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Functional Description
V1.0, 2010-02-19
TDA5235