th58nvg1s3aft05 TOSHIBA Semiconductor CORPORATION, th58nvg1s3aft05 Datasheet - Page 15

• Manufacturer Part Number: th58nvg1s3aft05
• Description: 2gbit 256m U 8bits Cmos Nand E2 Prom
• Manufacturer: TOSHIBA Semiconductor CORPORATION

PIN FUNCTIONS
pin-outs are configured as shown in Figure 1.
The device is a serial access memory which utilizes time-sharing input of address information. The device
Command Latch Enable: CLE
operation mode command into the internal command register.
The command is latched into the command register from the
I/O port on the rising edge of the WE signal while CLE is
High.
Address Latch Enable: ALE
information or input data into the internal address/data
register.
ALE is High.
Chip Enable:
operation, and will not enter Standby mode even if the CE input goes High.
Write Enable:
Read Enable:
I/O Port: I/O1 to 8
the device.
Write Protect:
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
in Busy state (
(
pulled-up to Vccq with appropriate resister..
CE signal is ignored when device is in Busy state (
RY
The CLE input signal is used to control loading of the
The ALE signal is used to control loading of either address
Address information is latched on the rising edge of WE if
Input data is latched if ALE is Low.
The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The
The WE signal is used to control the acquisition of data from the I/O port.
The RE signal controls serial data output. Data is available t
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
The
/
BY
RY
= H) after completion of the operation. The output buffer for this signal is an open drain and has to be
/
BY
RY
RY
RE
output signal is used to indicate the operating condition of the device. The
WE
CE
WP
/
BY
/
BY
= L) during the Program, Erase and Read operations and will return to Ready state
RY
/
BY
L ), such as during a Program or Erase or Read
REA
RY
GND
after the falling edge of RE .
CLE
ALE
/
WE
WP
CE
V
NC
NC
NC
NC
NC
BY
RE
NC
NC
V
NC
NC
NC
NC
NC
NC
NC
CC
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TH58NVG1S3AFT05
Figure 1. Pinout
2003-05-19A
RY
/
BY
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
signal is
15/32
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
NC
V
V
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
CC
SS