th58nvg1s3aft05 TOSHIBA Semiconductor CORPORATION, th58nvg1s3aft05 Datasheet - Page 24

• Manufacturer Part Number: th58nvg1s3aft05
• Description: 2gbit 256m U 8bits Cmos Nand E2 Prom
• Manufacturer: TOSHIBA Semiconductor CORPORATION

APPLICATION NOTES AND COMMENTS
(1) Power-on/off sequence:
(2) Status after power-on
(3) Prohibition of unspecified commands
(4) Restriction of command while Busy state
CE , WE , RE
sequence. During the initialization the device Ready/Busy signal outputs Busy state as shown in the
Figure-15. In this time period, the acceptable commands are FFh or 70h.
is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
Ready/Busy
The timing sequence shown in Figure 15 is necessary for power-on/off sequence.
The device internal initialization start after the power supply reaches appropriate level in power on
The WP signal is useful for protecting against data corruption at power-on/off.
The following sequence is necessary because some input signals may not be stable at power-on.
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3
During Busy state, do not input any command except 70H, and FFH.
CLE, ALE
WP
0 V
V
CC
Power on
invalid
V
don’t
care
100µs max
IL
2.5V
2.7V
1ms max
Reset
FF
Figure 16.
Figure 15. Power-on/off Sequence
V
IH
Operation
TH58NVG1S3AFT05
2003-05-19A
don’t
don’t
care
care
V
IL
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