th58nvg1s3aft05 TOSHIBA Semiconductor CORPORATION, th58nvg1s3aft05 Datasheet - Page 18

• Manufacturer Part Number: th58nvg1s3aft05
• Description: 2gbit 256m U 8bits Cmos Nand E2 Prom
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RY
DEVICE OPERATION
RY
Select page
Select page
CLE
RE
ALE
CLE
/
ALE
WE
WE
Read Mode
commands, start address for the Read mode need to be issued. Refer to Figure 3 below for sequence and the
block diagram (Refer to the detailed timing chart.).
RE
Random Column Address Change in Read Cycle
/
I/O
CE
BY
I/O
CE
BY
N
Read mode is set when "00H" and “30H” commands are issued to the Command register. Between the
N
Figure 4. Random Column Address Change in Serial Read
00H
00H
Col. M
M
Figure 3. Read mode (1) operation
Start-address input
Column Address M
M
Page N
Start-address input
M’
30H
Page Address N
Busy
2111
Start from Col. M
Cell array
Cell array
M
Col. M
M+1 M+2 M+3
Page N
30H
starts on the rising edge of WE in the 30h command input cycle
(after the address information has been latched). The device will
be in Busy state during this transfer period.
Serial data can be output synchronously with the RE clock from
the start address designated in the address input cycle.
can be changed by inputting the column address with 05h and
E0h commands.
is input to the device by 05h and E0h commands with /RE clock.
A data transfer operation from the cell array to the register
After the transfer period the device returns to Ready state.
In the serial data out from the register, the column address
The data are read out in serial from the column address which
05H
Busy
Col. M’
TH58NVG1S3AFT05
E0H
M
2003-05-19A
Page Address N
Start from Col. M’
M+1
M’ M’+1 M’+2 M’+3 M’+4
M+2
Page N
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