ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 133

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

(57)DLCR0
B7–B2 : Reserved bits. Do not change the initial values.
B1 : Download circuit access control register
B0 : Download circuit activation control register
(58) DLCR1
B7–B0 : Download address setting register 0
(59) DLCR2
B7–B0 : Download address setting register 1
OKI Semiconductor
setting can be
setting can be
setting can be
Mode where
Mode where
Mode where
Initial value
Initial value
Initial value
0 : PRAM access mode
1 : DRAM access mode
0 : Stop
1 : Activate
When writing data to PRAM/DRAM, set the start address of PRAM/DRAM (lower 8 bits: A7–A0) into this
register.
When writing data to PRAM/DRAM, set the start address of PRAM/DRAM (upper 8 bits: A15–A8) into this
register.
Also, when in the PRAM access mode, the address (DL_A[15:0]) is automatically incremented each time data
is written to the download data buffer register 2 (DL_BUF[23:16])
Furthermore, when in the DRAM access mode, the address (DL_A[15:0]) is automatically incremented each
time data is written to the download data buffer register 1 (DL_BUF[15:8]).
changed
changed
changed
DLCR0
DLCR1
DLCR2
DL_
DL_
A15
B7
B7
A7
B7
⎯
D/
D/
#
0
0
0
DL_
DL_
A14
B6
B6
A6
B6
⎯
D/
D/
#
0
0
0
DL_
DL_
A13
B5
B5
A5
B5
⎯
D/
D/
#
0
0
0
DL_
DL_
A12
B4
B4
A4
B4
⎯
D/
D/
#
0
0
0
DL_
DL_
A11
B3
B3
A3
B3
D/
D/
⎯
#
0
0
0
DL_
DL_
A10
B2
B2
A2
B2
⎯
D/
D/
#
0
0
0
SEL
DL_
DL_
DL_
B1
B1
A1
B1
A9
D/
D/
D/
0
0
0
FEDL7224-001FULL-01
ML7224-001TC
DL_
DL_
DL_
EN
B0
B0
A0
B0
A8
D/
D/
D/
0
0
0
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R/W
R/W
R/W
R/W
R/W
R/W