ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 43

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

(5) DSP Firmware Download Function
A. Overview
B. Control Registers for Download
C. Download Control Flow
OKI Semiconductor
This LSI has internal registers for downloading the DSP firmware: DLCR0a–DLCR5a on the DSP_A side, and
DLCR0b–DLCR5b on the DSP_B side. Download the DSP firmware by accessing these registers via a parallel
bus interface or serial control interfaces.
See the section describing control registers.
Figures 19 and 20 show control flows for downloading the DSP firmware.
Note that it is necessary to download the DSP firmware (write to PRAM/DRAM) for each of the DSP_A side
and DSP_B side.
If hardware power down is canceled (PDNB = “0”→“1”), this LSI is activated in the DSP power-down state
(DSP_RESET_a = 1, DSP_RESET_b = 1). Activate the download circuit in this state, write data to PRAM, and
write to DRAM. Once writing is complete, stop the download circuit, and cancel the DSP power down state
(DSP_RESET_a = 0, DSP_RESET_b = 0).
Succeedingly, the DSP firmware performs error check of written data, and the check result is stored in
DL_ST[2:0]a (CR5a-B[6:4]) and DL_ST[2:0]b (CR5b-B[6:4]). However, if the DSP firmware has not been
written normally, it is possible that the error check of written data itself may not finish. Therefore, monitor a
certain time period (1 sec) or longer from the cancellation of a DSP power down state outside the LSI. If the
result of an error check is not posted after a certail time period has elapsed, set to DSP power down state, and
write the DSP firmware again.
If the DSP firmware has been written normally, after the completion of an error check, both the initial mode
display register_a (READYa) and initial mode display register_b (READYb) are set to “1”, thus a initial mode
state is entered. Make various settings to the internal data memories and control regisers when in the initial
mode, and set both the operation start control register_a (OPE_STATa) and operation start control register_b
(OPE_STATb) to “1”. Once initialization inside the LSI is complete, both the initial mode display register_a
(READYa) and initial mode display register_ b (READYb) are cleared to “0”, thus, transitioning to the normal
operation mode
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