ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 55

• Manufacturer Part Number: ml7084-001
• Description: 4ch Voip Codec
• Manufacturer: Oki Semiconductor

• Valid write period WE_DCn (CH10& CH1)
WE_DC1 (CH0 & CH1)
WE_DC2 (CH0 & CH1)
WE_DCn (CH0 & CH1) n = 3, 4, 5, ……
*1:
It is prohibited to make a transition to a single-channel operation (SC_CH0EN=0 & SC_CH1EN=1 or
SC_CH0EN=1 & SC_CH1EN=0) before the decode output start offset time elapses after DEC_OUTON is set to
“1”.
Simultaneously with SC_CH0EN = SC_CH1EN=“1” (which activates speech codec CH0 & CH1), DEC_OUTON
can also be set to “1”.
However, in this case, set in advance so that the internal data memory for controlling the decode output start offset
time (DEC_ONTIM) is between 0010h (2.0 ms) and 0100h (32 ms).
Upon both completion of writing the first received data (CH0 & CH1) and elapse of the above offset time after
starting a speech codec, the decoder starts decode output.
• Receive error processing
Note:
This operational description is pertaining to the case of the 10 ms mode; in the 20 ms mode, the valid read period and
valid write period are as follows:
Valid read period RE_DCn (CH0 & CH1)
Valid write period WE_DCn (CH0& CH1)
OKI Semiconductor
The following describes the operation when receive data is written in the order of CH0 to CH1.
Write CH0 receive data (80 bytes) by the first receive data write request (FR1 = 1&RXREQ_First = 1).
Also, before starting to write CH0 receive data, by setting the receive data write channel notification register
(RXFLAG) to “0”, notify this LSI that CH0 receive data will be written. Once the writing of the CH0 receive
data is finished, the second receive data write request (FR1 = 1 & RXREQ_First = 0) will be made.
Write CH1 receive data (80 bytes) by the second write request. Also in this case, before starting to write CH1
receive data, by setting the receive data write channel notification register (RXFLAG) to “1”, notify this LSI
that CH1 receive data will be written. Note that, regardless of the first or second time, FR1 is set to “1” when a
receive data write request is made.
There is no time limit for the first valid write period after starting a speech codec (CH0 & CH1).
If only the tWAIT wait time has elapsed after completion of writing received data of CH0 and CH1, the decode
output control register (DEC_OUTON) can be set to “1”. The decoder starts decode output the tDECON time
after DEC_OUTON is set to “1”
(tWAIT = 2.0 ms, tDECON = 0 ms [initial value]
data memory.)
The second valid write period will be 2.0 ms.
The third valid write period and succeeding ones will be 9 ms.
Finish writing CH0 receive data and CH1 receive data within the valid write period.
If a write from the MCU side does not finish within the valid write period, the receive error of the applicable
channel (CH0: RXERR_CH0, CH1: RXERR_CH1) will be set to “1”. The receive error will be held until
immediately before the frame during which the receive data of the applicable channel has normally been written
is terminated in the succeeding valid write periods. If an error occurs, generated data is output according to the
PLC (Packet Loss Concealment) algorithm defined in G.711 Appendix I. However, the decoder outputs silence
data if the G.711 PLC function is disabled. Also, if the receive data of the same channel is written within one
frame, the invalid-write-on-the-receive-side error (RXBW_ERR) is set to “1”. RXBW_ERR will be held until
immediately before the frame during which invalid receive data has no longer been written is terminated in the
succeeding valid write periods.
Finish reading the CH0 and CH1 transmit data within 18.0 ms after the CH0 transmit data read request
(FR0_CH0=0) is generated.
(*1)
.
• • •
Can be set in the range of 0.0 ms to 32 ms in the internal
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