cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 110

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

The CX28560 Memory Organization
5.3.2
5.3.2.1
5.3.2.2
5-20
Interrupt Handling
Initialization
Interrupt management resources are automatically reset upon the following:
The CX28560 uses two interrupt queues. One is internal to CX28560 and is controlled
exclusively by the DMA block. The other is the Interrupt Queue in shared memory,
which is allocated and administered by the host, and written to (filled) by the
CX28560.
Upon initialization, the data in the status descriptor is reset to all 0s, indicating the
first location for next descriptor, the queue is not full, and no descriptors are currently
in the queue. Any existing descriptors in the internal queue are discarded.
The host must allocate sufficient shared memory space for the Interrupt Queue. Up to
64 K dwords of queue space are accessible by the CX28560, setting the upper limit
for the queue size. The CX28560 requires a minimum of two quadwords of queue
space. This sets the lower limit for the queue size.
The host must store the pointer to the queue and the length in quadwords of the queue
in the CX28560 within the Interrupt Queue Descriptor registers. Issuing the
appropriate Host service to the CX28560 can do this. As the CX28560 takes in the new
values, it automatically resets the controller logic as indicated above. This mechanism
can also be used to switch interrupt queues while the CX28560 is in full operation.
Interrupt Descriptor Generation
Interrupt conditions are detected in both error and non-error cases. CX28560 makes a
determination based on channel and device configuration whether reporting of the
condition is to be masked or whether an Interrupt Descriptor is to be sent to the Host.
If the interrupt is not masked, CX28560 generates a descriptor and stores it internally
prior to transferring it to the Interrupt Queue in shared memory.
The internal queue is capable of holding 512 descriptors while CX28560 arbitrates to
master the PCI bus and transfer the descriptors into the Interrupt Queue in shared
memory.
As the PCI bus is mastered and after descriptors are transferred out to the shared
memory, CX28560 updates the Interrupt Status Descriptor. When CX28560 updates the
WRPTR field in the Interrupt Status Descriptor, it asserts the PCI INTA# signal line.
If during the transfer of descriptors, the Interrupt Queue in shared memory becomes
full, CX28560 stops transferring descriptors until the Host indicates more descriptors
can be written out. CX28560 indicates that it cannot transfer more descriptors into
shared memory by setting the bit field INTFULL in the Interrupt Status Descriptor.
In cases where the internal queue is full (either because the Host queue is full or there
was not enough PCI bandwidth) and new descriptors are generated, the new
descriptors are discarded. CX28560 indicates it has lost interrupts internally by
overwriting the bit field ILOST in the last Interrupt Descriptor in the internal queue.
The ILOST indication represents one or more lost descriptors.
Hardware reset
Soft reset
Write to Interrupt Queue Pointer by a direct PCI write
Write to Interrupt Queue Length by a direct PCI write
Mindspeed Technologies™
Advance Information
CX28560 Data Sheet
28560-DSH-001-B