cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 81

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
4.5
4.6
28560-DSH-001-B
Interrupt Controller
Serial Port Interface Definition in Conventional Mode
The Interrupt Controller takes receive and transmit events/errors from RxSIU,
RxSLP, RxBUFFC, and TxSIU, TxSLP, and TxBUFFC respectively. The
Interrupt Controller coordinates the transfer of internally queued descriptors to an
interrupt queue in shared memory, and coordinates notification of pending
interrupts to the host.
A Receive Serial Port Interface (RSIU) connects to four input signals: RCLK,
RDAT, RSYNC, and ROOF. A Transmit Serial Port Interface (TSIU) connects to
three input signals and one output signal: TCLK, TSYNC, TCTS, and TDAT,
respectively. The SIU receives and transmits data bytes to the Transmit Serial
Line Processor (TSLP) and the Receive Serial Line Processor (RSLP). The
receive and transmit data and synchronization signals are synchronous to the
receive and transmit line clocks, respectively.
The CX28560 can be configured to sample in and latch out data signals, and
sample in status and synchronization signals on either the rising or falling edges
of the respective line clock, namely RCLK and TCLK. This configuration is
accomplished by setting the ROOF_EDGE, RSYNC_EDGE, RDAT_EDGE,
TSYNC_EDGE, and TDAT_EDGE bit fields. The default, after reset, is to
sample in and latch out data synchronization and status on the falling edges of the
respective line clock.
The port mode is configured by programming the RPORT_TYPE and
TPORT_TYPE bit fields. When configured to operate in conventional mode, the
receive and transmit directions are not related to each other, so each direction can
be programmed independently of the other.
Mindspeed Technologies™
Advance Information
CX28560 Serial Interface
4
-
7