cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 66

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Expansion Bus (EBUS)
Table 3-2. EBUS Service Request Field Descriptions
3-4
Number
dword 0
dword 1
dword 2
Dword
EBUS Base Address
EBUS Byte Enable
Descriptor Field
Shared Memory
FIFO_BURST
SACKIEN
Reserved
OPCODE
Pointer
Length
Offset
(EBE)
(Bits)
Size
14
32
32
5
1
7
1
4
Mindspeed Technologies™
Value
—
—
—
—
—
6
7
0
0
1
Advance Information
EBUS Write command (EBUS_WR)
EBUS Read command (EBUS_RD)
Enable (1) or disable (0) acknowledge via interrupt in the end of the
command execution
Reserved bits should be written with 0s.
Do increment EBUS address (address on the target device) by one
after each EBUS access. This is used to access a continuous segment
or block of memory on the target device that is connected to the EBUS.
Do not increment EBUS address for this access. On some devices,
memory accesses are carried out the writing/reading of one memory
location. By setting FIFO_BURST to one, CX28500 does not increment
the EBUS address after an access. Hence, the address stays the same
for the next EBUS access.
The value driven over EBE[3:0]*. Each bit controls a corresponding
byte access on the EBUS. For example, an EBE[3:0] value of 0001
means that Host data passes to the device attached to the EBUS on
byte 0, the least significant byte, of the EBUS while the other three
bytes are inaccessible.
Number of EBUS transactions.
The Shared Memory Pointer (Buffer Address) is a dword–aligned
address of the first buffer to or from which data needs to be
transferred from or to the EBUS. The two LSB’s must be equal to zero
for dword alignment.
The EBUS Base Address Offset is the address for the first EBUS
transaction.
Description
CX28560 Data Sheet
28560-DSH-001-B