cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 92

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

The CX28560 Memory Organization
5-2
layout is given in
first one includes the registers that are directly accessed by the host through the PCI
(direct access) and the second includes the registers that are accessed through the
Service Request Mechanism (indirect access).
The only registers that can be directly accessed by the host as slave reads or writes are
the Rx Port Alive, the Tx Port Alive, the Interrupt Status Descriptor, the Interrupt
Queue Pointer, the Interrupt Queue Length, the Service Request Length, the Service
Request Pointer, and the Soft Reset registers. These are specified in
the host writes directly into a corresponding register, the CX28560 behaves as a PCI
slave while this write is performed.
All other registers need to be accessed through the Service Request Mechanism. After
the PCI reset, when the CX28560 is ready for configuration, these registers are
updated with the appropriate shared memory values through a Configuration Write
Service Request. After the host has configured the shared memory image of the
CX28560’s registers, and the CX28560 has finished its local configuration (i.e.,
SRQ_LEN bit field in Service Request Length is reset to zero by the CX28560), the
host issues a service request by writing directly into the Service Request Length
register. Writing to this location the actual value of the Service Request Descriptor
Table Length from shared memory causes the CX28560 to start performing the
Service Request Descriptor Table.
Mindspeed Technologies™
Table
Advance Information
5-1. It should be noted that there are two address spaces. The
Table
CX28560 Data Sheet
28560-DSH-001-B
5-1. When