cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 69

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
3.1.8
28560-DSH-001-B
Microprocessor Interface
The MPUSEL bit field in EBUS Configuration register specifies the type of
microprocessor interface to use for the EBUS.
If Intel-style protocol is selected, the following signals are effective:
If Motorola-style protocol, the following signals are effective:
• ALE*
• RD*
• WR*
• HOLD
• HLDA
• AS*
• DS*
• R/WR*
• BR*
• BG*
• BGACK*
the address lines contain a valid address. This signal remains asserted for the
duration of the access cycle.
device and is held high during writes.
device and is held high during reads.
EBUS from a bus arbiter.
signal assertion. Remains asserted until after the HOLD signal is deasserted. If
the EBUS is connected and there are no bus arbiters on the EBUS, this signal
must be asserted high at all times.
lines contain a valid address. This signal remains asserted for the duration of
the access cycle.
writes for the addressed device.
throughout write operation by the CX28560. This signal determines the
meaning (read or write) of DS*.
from a bus arbiter.
signal assertion. Remains asserted until after the BR* signal is deasserted. If
the EBUS is connected and there are no bus arbiters on the EBUS, this signal
must be asserted low at all times.
detects BGACK* currently deasserted. As this signal is asserted, the CX28560
begins the EBUS access cycle. After the cycle is finished, this signal is
deasserted indicating to the bus arbiter that the CX28560 has released the
EBUS.
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Mindspeed Technologies™
Address Strobe, driven low by the CX28560 to indicate that the address
Data Strobe, strobed low by the CX28560 to enable data reads or data
Bus Request, asserted low by the CX28560 when it requests the EBUS
Read, strobed low by the CX28560 to enable data reads out of the
—
—
Hold Acknowledge, asserted low by bus arbiter in response to BR*
Write, strobed low by the CX28560 to enable data writes into the
—
Address Latch Enable, asserted low by the CX28560 to indicate that
Hold Request, asserted high by the CX28560 when it requests the
Hold Acknowledge, asserted high by bus arbiter in response to HOLD
Read/Write, held high throughout read operation and held low
—
Bus Grant Acknowledge, asserted low by the CX28560 when it
Advance Information
Expansion Bus (EBUS)
3
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