cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 37

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
Table 1-6. Serial Interface (General) (2 of 3)
28560-DSH-001-B
ROOF[31:0]/
CTS [31:0]/
TSTB[31:0]
RCLK[31:0]
Pin Name
I/O
I
I
TCLK[31:0]/
RCLK[31:0]
—
Ref Clk
This pin has three separate definitions. Control of the use of the pin is configured in the
Table 5-39, RSIU Port Configuration Register
using the CTSENB and ROOFABT fields.
(2)(3)(5) Receiver Out-Of-Frame ROOF[31:0]. If the pin is configured to be ROOFx, it is
sampled on the configured active edge of the corresponding receive clock RCLKx. If
ROOFx signal performs a transition from low to high (assertion), an Out-Of-Frame
(OOF) condition interrupt is generated if the interrupt is enabled. While ROOFx is
asserted, the received serial data stream is considered Out-Of-Frame. If OOFABT bit
field is configured to 1, the receive channel processing is disabled for the entire port
and it remains disabled until ROOFx is deasserted; otherwise, the receive channel
processing is enabled. Upon ROOFx deassertion, if OOFIEN bit field is set to 1, an
interrupt Frame Recovery (FREC) is generated. The data processing resumes for all
affected channels.
General Interrupt Line. This signal can also operate as a general Serial Port Interrupt
(SPORT) by clearing the OOFABT bit field and setting the OOFIEN bit field (i.e., OOFABT
= 0 and OOFIEN = 1). When the ROOFx signal transitions from high-to-low
(deassertion), a SPORT interrupt is generated and data stream is not affected. If this
signal is used as a general purpose interrupt, no interrupt is generated until this signal
goes from high to low.
(2)(3)(5) Channel Clear To Send (CTS[31:0]). If CTSx, the signal is sampled on the
specified active edge of the corresponding transmit clock, TCLKx. If CTS transitions
from high-to-low (is deasserted), the channel assigned to the time slot sends
continuous idle characters after the current message has been completely transmitted.
The message transmission data restarts when this CTS transitions from low to high
again (is asserted). The response time to CTS is a 32 bit-time, meaning that a new
message might be transmitted if the message starts within the next 32 bits after CTS
was deasserted.
(2)(4)(5) TSBUS Strobe (TSTB[31:0]) If the port is configured in TSBUS mode the this
pin is used as TSTBx. The signal is sampled twice, once by the receive circuitry on the
specified edge of the corresponding receive clock, RCLKx, and once by the transmit
circuitry on the specified edge of the corresponding transmit clock, TCLKx.
If TSTB transitions from low to high, it marks the first bit of time slot 0 within the
TSBUS frame. Because there is a single TSTB for both directions, receive and transmit,
the number of configured time slots and the RPORT_TYPE or TPORT_TYPE value
specifying whether the serial port operates in TSBUS or non-TSBUS mode must be
identically configured for both directions per serial port. Unexpected CX28560 behavior
may be generated if this restriction is violated.
Receive Clock (RCLK[31:0]). This clock controls the rate at which data is received and
synchronizes sampling of RDATx, RSYNCx (non-TSBUS mode only), RSTUFFx (TSBUS
mode only), and TSTBx (TSBUS mode only, and only for receive path circuitry).
If in TSBUS (with DS0 extraction) mode, RCLKx also synchronizes transitions of
RGSYNCx.
Mindspeed Technologies™
Advance Information
Description
and
Table 5-53, TSIU Port Configuration Register
Introduction
1
-
19