cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 151

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
6.1.2.7
6.1.2.8
28560-DSH-001-B
Channel and Port Configuration
Typical Initialization Procedure
After general configuration, a specific channel and port configuration must be
performed for each supported channel and port.
Channel operations service request commands are:
This section depicts a typical initialization procedure.
NOTE:
• Receive BUFFC Flexiframe Memory
• Transmit BUFFC Flexiframe Memory
• Receive BUFFC Channel Configuration Register
• Receive SLP Channel Configuration Register
• Receive SIU Time Slot/Group Map
• Receive SIU Group Map
• Receive SIU Group State Register
• Receive SIU Time Slot/Group Map Pointer Allocation Register
• Receive SIU Port Configuration Register
• Transmit BUFFC Channel Configuration Register
• Transmit SLP Channel Configuration Register
• Transmit SIU Time Slot/Group Map
• Transmit SIU Group Map
• Transmit SIU Group State Register
• Transmit SIU Time Slot/Group Map Pointer Allocation Register
• Transmit SIU Port Configuration Register
• CH_ACT: Channel Activate
• CH_DEACT: Channel Deactivate
1.
2.
3.
4.
5.
6.
PCI Reset or Soft Chip Reset (a Soft Chip Reset is performed by a direct
write to the CX28560 register map—in the Soft Chip Reset register)
After performing a Soft Chip Reset, it is not necessary to reconfigure the
PCI.
PCI configuration.
Allocate areas in the shared memory for:
a.
b.
c.
Loop and wait for the Service Request Length register to be ready. This
step confirms that the CX28560 completed its internal initialization.
a.
b.
c.
Initialize the Interrupt Queue Pointer register and Interrupt Length register
by performing a direct write to the CX28560 registers with the address of
the Interrupt Queue located in the shared memory and its length.
Check the port alive availability (i.e., TxPortAlive and RxPortAlive)
register by performing direct reads. For each active port the correspondent
bit in TxPortAlive and RxPortAlive registers must be set to 1.
a.
b.
c.
Mindspeed Technologies™
Interrupt Queue
Service Request Table
The CX28560’s configuration registers (global and local per channel/
port/TS basis).
Read the SRQ_LEN through the PCI slave access and check if it is 0.
If true, go to the next step.
Otherwise continue to check.
While port not alive (this is equivalent with the correspondent bit not
set) wait 8–16 serial clocks.
If port not alive, poll until port alive.
Otherwise go to the next step.
Advance Information
Functional Description
6
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5