cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 24

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Introduction
1.2
1.2.1
1.2.1.1
1-6
System-Side Interfaces
POS-PHY Interfaces
POS-PHY Data Interface—CX28560
Data is transferred between the System and the CX28560 over a bidirectional
standard POS-PHY level 3 100 MHz, 32-bit interface, working in packet mode. The
data is transferred as fragments accompanied by a 4-byte fragment header.
Data transferred on this POS-PHY interface is in fragments of a user- configurable
length (minimum 32 bytes, maximum 256 bytes) together with a fragment header (4
bytes).
As the fragment length increases, the number of configurable channels decreases.
When 56-byte fragments are used, up to 2047 channels may be configured; when 112-
byte fragments are configured, a maximum of 1024 channels may be configured. See
Appendix I
channels, and the channels’ bandwidths.
The last fragment of each message is marked as an End Of Message (EOM) fragment.
The next message starts with the fragment immediately following an EOM fragment.
The receive fragment header contains the following fields:
The transmit fragment header contains the following fields:
For fragment header formats see
header layout.
• Channel Number
• Fragment Length
• End of Message Indicator
• Beginning of Message Indicator
• Message Status
• Channel Number
• Command Valid
• Idle Code (IC) select (HDLC Flags/Aborts, All Zeros) for padding between
• Pad Count (PADCNT) minimum number of idle codes to be inserted after
• Abort Command
messages
message
for an explanation of the relationship between fragment length, number of
Mindspeed Technologies™
Advance Information
Chapter
5.0, POS-PHY transaction headers for full
CX28560 Data Sheet
28560-DSH-001-B