cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 40

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Introduction
Table 1-8. CX28560 POS-PHY Interface (Transmit) (2 of 2)
1-22
PTPA
TPRTY
Note(s):
The following pins are supported by the standard POS-PHY, but are not required because the CX28560 supports only packet-level
transfers on a single PHY basis:
Transmit Start of Transfer (TSX) signal;
Transmit PHY Address (TADR[]) bus;
Direct Transmit Packet Available (DTPA[]);
Selected-PHY Transmit Packet Available (STPA) signal.
Pin Name
I/O
O
I
TFCLK
TFCLK
Ref Clk
Transmit Packet Available (PTPA) signal. PTPA transitions high when a predefined
minimum number of bytes are available in the polled transmit FIFO. Once high, PTPA
indicates that the transmit FIFO is not full. When PTPA transitions low, it optionally
indicates that the transmit FIFO is full or near full. PTPA allows the polling of the
CX28560. The port which PTPA reports is updated on the following rising edge of
TFCLK. PTPA is updated on the rising edge of TFCLK.
Transmit Bus Parity Signal (TPRTY). TPRTY indicates the parity calculated over the
TDAT bus. TPRTY is considered valid only when TENB is asserted. The CX28560
supports odd parity checking which can be disabled by configuring the DISBLPAR bit in
the
parity error to the system, but shall not interfere with the transferred data.
Mindspeed Technologies™
Table 5-21, Transmit POS-PHY Thresholds
Advance Information
Description
Register.The CX28560 reports any
CX28560 Data Sheet
28560-DSH-001-B