cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 187

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
8.2.4
Table 8-11. EBUS Reset Parameters
Table 8-12. EBUS Input/Output Timing Parameters
28560-DSH-001-B
T
NOTE(S):
(1)
T
T
T
T
T
NOTE(S):
(1)
(2)
off
on
off
val
ds
dh
Symbol
Symbol
For purposes of active/float timing measurements, the hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
Minimum and maximum times are evaluated at 40 pF equivalent load. Actual test capacitance may vary, and results should be
correlated to these specifications.
For purposes of active/float timing measurements, the hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification at 40 pF equivalent load.
ECLK to Signal Valid Delay
Float to Active Delay
Active to Float Delay
Input Setup Time to Clock
Input Hold Time from Clock
Active to Inactive Delay
Expansion Bus (EBUS) Timing and Switching Characteristics
The EBUS timing is derived directly from the PCI clock (PCLK) input into CX28560.
The EBUS clock can have the same frequency as the PCI clock, or it can have half the
frequency of the PCI clock.
Figure 8-6. EBUS Reset Active to Inactive Delay
NOTE(S):
Parameter
(2)
(2)
Parameter
(1)
The EBUS reset is dependent on the PRST* (PCI Reset) signal being asserted low.
(
1)
Mindspeed Technologies™
Three-state
Output
EBUS
EBUS
Advance Information
Reset
Input
PCI
Min
—
–0.5
Min
—
18
2
1
T
off
Max
Electrical and Mechanical Specification
28
Input Ignored
Reset Period
Max
4.5
—
28
—
—
Three-state
Units
Units
ns
ns
ns
ns
ns
ns
8
-
11