cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 52

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cx28560

Manufacturer Part Number
cx28560
Description
Hdlc Controller
Manufacturer
Mindspeed Technologies
Datasheet
Host Interfaces
Table 2-1. PCI Configuration Space
2-6
Register
Number
12–14
5–10
11
15
0
1
2
3
4
Byte Offset
(hex)
00h
04h
08h
0Ch
10h
2Ch
3Ch
The Base Code register contains the Class Code, Sub Class Code, and Register Level
Programming Interface registers.
All writable bits in the configuration space are reset to 0 by the hardware reset,
PRST* asserted. After reset, the CX28560 is disabled and only responds to PCI
configuration write and PCI configuration read cycles. Write cycles to reserved bits
and registers have no effect. Read cycles to reserved bits always result in 0 being read.
31
Max Latency
Reserved
Mindspeed Technologies™
24
Subsystem ID
Device ID
Status
Advance Information
23
Header Type
The CX28560 Base Address Register
Base Code
Min Grant
Table 2-1
16
Reserved
Reserved
illustrates the PCI Configuration Space.
15
Latency Timer
Interrupt Pin
Subsystem Vendor ID
8
Command
Vendor ID
7
Interrupt Line
Revision ID
CX28560 Data Sheet
Reserved
28560-DSH-001-B
0

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