mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 106

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 FlexRay Communication Controller
0 – The slot status counter is incremented independently of the null frame indication bit.
1 – The slot status counter is incremented only when a syntactically correct null frame is received.
SYNCFS — SYNC Frame Selection
This register can be used to restrict counting to received sync frames only.
0 – The slot status counter can be incremented independently of the sync frame bit.
1 – The slot status counter can be incremented only when a syntactically correct sync frame is received.
SUPFS — StartUP Frame Selection
This register can be used to restrict counting to received startup frames only.
0 – The slot status counter can be incremented independently of the startup bit.
1 – The slot status counter can be incremented only when a syntactically correct startup frame is received.
VCES — Valid Communication Element Selection
This register can be used to restrict counting to semantically valid frames only.
0 – The slot status counter can be incremented for semantically valid and invalid frames.
1 – The slot status counter can be incremented only when a semantically valid frame is received.
MULTCYC — Multiple Cycle
This bit determines if the slot status counter reflects the values of multiple communication cycles or of the
previous communication cycle only. Note that MULTCYC may be written during normal operation, but its
value must not be modified by the host during the NIT.
0 – The internal slot status counter starts at 0 at the beginning of every communication cycle, and SSCnR
reflects the values of the previous communication cycle.
1 – The internal slot status counter is not reset to 0 at the beginning of every communication cycle; this
allows counting of specific slot status conditions over several communication cycles. SSCnR reflects the
accumulated values counted in previous communication cycles.
CHCFG1, CHCFG0 — Channel Configuration
These bits determine the channel assignment for slot status counters SSCnR, as defined in
106
CHCFG1
0
0
CHCFG0
Table 3-6. Channel Configuration for SSCCnR
0
1
Count for channel A
Count for channel B
MFR4200 Data Sheet, Rev. 0
Meaning
Freescale Semiconductor
Table
3-6.