mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 156

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 FlexRay Communication Controller
Transmit message buffer:
The content of the buffer is transmitted only on the channels specified in the channel filtering field when
the cycle counter filtering and frame ID filtering criteria are also met.
Receive FIFO:
Those bits have no meaning for the receive FIFO (refer to
information about FIFO filters)
3.4.1.7
The host controls the cycle counter filtering (refer to
n = [0:58]
1 – Cycle counter filtering is enabled.
0 – Cycle counter filtering is not performed.
3.4.1.8
DATUPD indicates if the frame data was or was not updated during the last matching slot/cycle/channel
triple in the static segment according to the filter. The CC updates the DATUPD bit after every static slot
assigned to this buffer. The host may reset this bit during the configuration state by writing a “0” to the bit.
Note that DATUPD is not reset by empty minislots in the dynamic segment. It is set, however, when a
semantically valid frame is received in the dynamic segment.
1 – A semantically valid (non null) frame was received during the last slot with a matching
slot/cycle/channel triple.
0 – Either a frame that was not semantically valid or a null frame was received during the last slot with a
matching slot/cycle/channel triple.
3.4.1.9
The host can configure every buffer of the CC as a single transmit message buffer or as a double message
buffer. The handling and the operations for buffers with different types are specified in
“Message Buffer Handling and
0 – Single transmit message buffer.
156
ChA
1
1
0
0
(CCFnR)”) of a buffer by the cycle counter filtering enable bit.
CCFE — Cycle Counter Filtering Enable Bit
DATUPD — Data Updated
BT — Buffer Type
ChB
1
0
1
0
Transmit message buffer
on both channels
Table 3-15. Channel Filtering Configuration
Transmit frame
no transmission
Operations”.
on channel A
on channel B
MFR4200 Data Sheet, Rev. 0
Section 3.2.3.8.4, “Cycle Counter Filter n Register,
Section 3.6, “Receive FIFO
Store semantically valid received frame
Receive message buffer
received on channel A
received on channel B
ignore frame
ignore frame
Freescale Semiconductor
Function” for more
Section 3.5,