mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 89

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.2.3.3.34
FlexRay Protocol Related Parameter – gOffsetCorrectionStart
Address 0xE0
Reset
This register defines the delay time (in multiples of macroticks) after which the offset correction will start.
Writing this register is possible only during the configuration state.
Freescale Semiconductor
CNTRL[7:4],
Reserved
CNTRL[3:0]
SOCCT7
rw*
15
7
r
13
14
15
undefined state
Table 3-3. Encoding of Debug Port Control Fields CNTRL[7:4] and CNTRL[3:0] (continued)
Start of Offset Correction Cycle Time Register (SOCCTR)
The time interval between the start time of the NIT (see NITCR) and the
Start of Offset Correction time is used by the CC for clock correction
calculations. The minimum interval that must be ensured during NITCR and
SOCCTR programming can be calculated from
Therefore, the SOCCTR value must be:
Reserved
Dynamic slot start on channel B
Start of frame on channel B
Received syntactically correct an semantically valid frame indication on channel B
SOCCT6
Delaymin = ceil(500µT + 110µT*MSFR)/NMLR) + 1 [nominal MT]
rw*
14
6
r
Figure 3-47. Start of Offset Correction Cycle Time Register
SOCCTR >= NITCR + Delaymin [nominal MT]
SOCCT13
SOCCT5
rw*
rw*
13
5
Mode of the BGT, Mode of the ARM_BG
MFR4200 Data Sheet, Rev. 0
SOCCT12
SOCCT4
rw*
rw*
12
4
NOTE
SOCCT11
SOCCT3
rw*
rw*
11
3
Equation
SOCCT10
SOCCT2
rw*
rw*
10
2
3-7:
SOCCT9
SOCCT1
Memory Map and Registers
rw*
rw*
9
1
Signal
DSSB
RCFB
SOCCT8
SOCCT0
SFB
Eqn. 3-7
Eqn. 3-8
rw*
rw*
8
0
89