mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 135

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.2.3.8.3
Address 0xF2
Reset
If the ENSYNFF bit is set (see
register is used to identify a sync frame ID whose arrival time measurement values are to be rejected for
clock synchronization. Note that this register can be written at any time by the host, unlike SYNFAFMR
and SYNFAFVR (see
and
3.2.3.8.4
Address CCF0R=0x202, CCF1R=0x206, …, CCF57R=0x2E6, CCF58R=0x2EA.
CCFnR=0x202 + 0x4*dec2hex(n)
Reset
Each cycle counter filter register is related to an appropriate message buffer: CCF0R to message buffer 0,
CCF1R to message buffer 1, … , CCF58R to message buffer 58. (For more information, refer to
“Receive, receive FIFO, and transmit message buffers are accessible to the host MCU only through the
active receive, active transmit, and active receive FIFO
Freescale Semiconductor
SYNFRF7
Reserved
Reserved
Reserved
Section 3.2.3.8.1, “Sync Frame Acceptance Filter Value Register
15
rw
15
7
7
r
r
r
undefined state
undefined state
Sync Frame Rejection Filter Register (SYNFRFR)
Cycle Counter Filter n Register, n = [0:58] (CCFnR)
To ensure correct operation of the CC, the host should update this register
only during the NIT.
SYNFRF6
Reserved
Reserved
Reserved
14
rw
14
6
6
r
r
r
Section 3.2.3.8.2, “Sync Frame Acceptance Filter Mask Register
Figure 3-109. Cycle Counter Filter n Register, n = [0:58]
Figure 3-108. Sync Frame Rejection Filter Register
SYNFRF5
Reserved
CCM5
CCV5
Section 3.2.3.2.1, “Module Configuration Register 0
rw*
rw*
13
13
rw
5
5
r
MFR4200 Data Sheet, Rev. 0
SYNFRF4
Reserved
CCM4
CCV4
rw*
rw*
12
12
rw
4
4
r
NOTE
SYNFRF3
buffers.”).
Reserved
CCM3
CCV3
rw*
rw*
11
11
rw
3
3
r
SYNFRF10
SYNFRF2
(SYNFAFVR)”).
CCM2
CCV2
rw*
rw*
10
rw
rw
10
2
2
SYNFRF9
SYNFRF1
Memory Map and Registers
CCM1
CCV1
(MCR0)”), this
rw*
rw*
rw
rw
9
1
9
1
(SYNFAFMR)”
SYNFRF8
SYNFRF0
Section ,
CCM0
CCV0
rw*
rw*
rw
rw
8
0
8
0
135