mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 54

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 FlexRay Communication Controller
3.1.2
3.1.2.1
3.1.2.2
3.2
3.2.1
This section describes the memory map, and the content and use of the registers in the host interface
module. A memory map of the CC is shown in
The host accesses four types of CC registers:
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The duration of a microtick (µT) is one CC_CLK period (25 ns at 40 MHz); a microtick starts with
a rising edge of CC_CLK.
The CC internal initialization procedure lasts for 1025 cycles of the CC_CLK clock; it starts after
leaving the hard reset state (see
After the external hard reset signal on the RESET# pin is negated, the CLKOUT signal frequency
is stabilized after 8 µT.
The maximum external clock frequency is 40 MHz (CC_CLK).
Minislot length down to 2 µs (at CC_CLK frequency of 40 MHz) for the dynamic segment.
Minislot length is configurable (minimum 2 MT).
The maximum communication cycle length is 16 ms.
Collision avoidance symbol length is set to 30 bits.
The maximum configurable static slot length is 255 MT.
General control registers
Buffer control, configuration, status and filtering register sets
FIFO acceptance/rejection filter register sets
Fifty-nine (59) configurable message buffers. The host can configure every buffer as a receive
message buffer, as a transmit message buffer (single or double), or as a FIFO receive message
buffer. All buffers are accessible through three active windows mirrored to the memory map:
— One active transmit message buffer
— One active receive message buffer
— One active FIFO buffer
Memory Map and Registers
MFR4200 Implementation Parameters and Constraints
Introduction
Implementation Parameters
Implementation Constraints
Refer to
information on the CLKOUT output.
Section 3.8, “External 4/10 MHz Output
Section 3.9.1, “Hard Reset
MFR4200 Data Sheet, Rev. 0
Table
NOTE
3-1.
Clock” for more
State”).
Freescale Semiconductor