mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 108

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 FlexRay Communication Controller
Via this register, the host may enable individually each bit in the SSCIR (see
Counter Incrementation Register
Section 3.2.3.6.6, “Interrupt Status Register 0
1 – If the corresponding bit in register SSCIR is set, trigger the interrupt SSINT.
0 – Ignore the corresponding bit in register SSCIR; do not trigger an interrupt.
3.2.3.6
3.2.3.6.1
Address 0x24
Reset
This register indicates the lowest numbered receive message buffer that has its interrupt status flag (IFLG)
and its interrupt enable (IENA) bits set. The register is cleared by a hard reset or by leaving the
configuration state.
108
Reserved
Reserved
15
7
r
r
0x0
Interrupt and Error Signaling Related Status Registers
Receive Buffer Interrupt Vector Register (RBIVECR)
•
•
•
Reserved
Reserved
14
After an IFLG has been set or cleared, the CC updates the RBIVECR
register after 1 µT.
The RBIVECR register contains valid data only if the RXIF bit is set
(see
If there are no IFLG bits set for any receive message buffers that have
their IENA bit set, then the CC sets the RBIVECR register to 0x0000
(IFLG, IENA — see
Configuration and Status n Register, n = [0:58]
6
r
r
Section 3.2.3.6.6, “Interrupt Status Register 0
Figure 3-73. Receive Buffer Interrupt Vector Register
Reserved
RBIVEC5
13
rh
5
r
(SSCIR)”) to trigger the interrupt SSINT in the ISR0 (see
Section 3.2.3.7.2, “Message Buffer Control,
MFR4200 Data Sheet, Rev. 0
Reserved
RBIVEC4
12
rh
4
r
(ISR0)”.
NOTE
Reserved
RBIVEC3
11
rh
3
r
(BUFCSnR)”).
Reserved
RBIVEC2
(ISR0)”).
10
rh
2
r
Section 3.2.3.5.9, “Slot Status
Reserved
RBIVEC1
Freescale Semiconductor
rh
9
1
r
Reserved
RBIVEC0
rh
8
0
r