ch7019 Chrontel, ch7019 Datasheet - Page 16

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
2.3
Multiplexed input data, sync and clock signals from the graphics controller inputs to the CH7019 through one of the two
12-bit variable voltage input ports, D1[11:0] or D2[11:0], and is directed to the TV data path. Non-multiplexed 24-bit
input data also inputs through both of the two input ports. Detailed descriptions of the eight input data formats are given
in Section 2.2. Clock signal (P-Out) outputs as a frequency reference to the graphics controller to ensure accurate
frequency generation. Horizontal and vertical sync signals are normally sent to the CH7019 from the graphics controller,
but can be optionally generated by the CH7019 and output to the graphics controller. Using the serial port, the CH7019
can be programmed as the clock master, clock slave, sync master or sync slave. Data will be 2X multiplexed (2x12 bits)
or non-multiplexed (1x24 bits), and the XCLK clock signal can be 1X or 2X times the pixel rate. The input data will be
encoded into the selected video standard, and output from the video DACs.
2.3.1
The CH7019 display mode is controlled by three independent factors: input resolution, TV format, and scale factor,
which are programmed via the display mode register. It is designed to accept input resolutions of 512x384, 640x480,
640x400, 720x400, 720x480, 720x576, 800x600, and 1024x768.
It is designed to support output to either NTSC or PAL television formats. The CH7019 provides interpolated scaling
with selectable factors of 5:4, 1:1, 7:8, 5:6, 3:4, 7:10 and 25:21 in order to support adjustable overscan or underscan
operation when displayed on a TV. The modes supported for TV-Out are shown in the Table 10 below.
2.3.2
The CH7019 integrates an advanced 2-line, 3-line, 4-line, 5-line, 6-line and 7-line (depending on mode) vertical
deflickering filter circuit to help eliminate the flicker associated with interlaced displays. This flicker circuit provides an
adaptive filter algorithm for implementing flicker reduction with selections of high, medium or low flicker content for
both luma and chroma channels (see register descriptions). In addition, a special text enhancement circuit incorporates
additional filtering for enhancing the readability of test. These modes are fully programmable via serial port interface
using the flicker filter register.
16
TV-Out
Table 10: TV Output Modes
512x384
512x384
720x400
720x400
640x400
640x400
640x480
640x480
720x480
720x480
720x576
720x576
800x600
800x600
1024x768
1024x768
Display Modes
Adaptive Flicker Filter
Resolution
Graphics
1
2
bypassed.
These DVD modes operate with interlaced input. Scan conversion and flicker filter are bypassed.
These DVD modes operate with non-interlaced input. Scan conversion and flicker filter are not
1
2
1
2
Active Aspect
Ratio
4:3
4:3
4:3
4:3
8:5
8:5
4:3
4:3
4:3
4:3
4:3
4:3
4:3
4:3
4:3
4:3
Pixel Aspect
1.35:1.00
1.35:1.00
15:12
15:12
Ratio
1:1
1:1
1:1
1:1
1:1
1:1
9:8
9:8
1:1
1:1
1:1
1:1
TV Output
Standard
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
201-0000-048
5/4, 1/1, 7/8, 25/21
5/4, 1/1, 5/6, 25/21
5/4, 1/1, 25/21
Scaling Ratios
3/4, 7/10, 5/8
1/1, 7/8, 5/6
1/1, 7/8, 5/6
1/1, 5/6, 5/7
1/1, 5/6, 5/7
5/7, 5/8, 5/9
5/8, 5/9, 1/2
5/4, 1/1
5/4, 1/1
5/4, 1/1
5/4, 1/1
1/1
1/1
Rev. 2.4, 12/18/2006
CH7019B