ch7019 Chrontel, ch7019 Datasheet - Page 4

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
1.2
4
Pin #
66, 101
65, 102
63, 104
62, 105
107
108
106
111
123-126, 56,
57
127
128
36
58
Table 1: Pin Description
Pin Description
1
1
1
1
# of Pins Type
2
2
2
2
1
1
6
1
1
In/Out
In/Out
In
Out
In/Out
In
In
In
In/Out
Out
Out
In
In
Symbol
H1, H2
V1, V2
DE1, DE2
FLD1,
FLD2
SPD
SPC
AS
VREF2
GPIO[5:0]
ENAVDD
ENABLK
VSWING
RESET*
Description
Horizontal Sync Input / Output
When the SYO control bit is low, these pins accept a horizontal sync inputs
for use with the input data. The amplitude will be 0 to VDDV. VREF1 is
the threshold level for these inputs. These pins must be used as inputs in
RGB Bypass mode.
When the SYO control bit is high, the TV encoder will output a horizontal
sync pulse 64 pixels wide to one of these pins. The output is driven from
the DVDD supply. This output is valid only when TV-Out is in operation.
Vertical Sync Input / Output
When the SYO control bit is low, these pins accept a vertical sync inputs
for use with the input data. The amplitude will be 0 to VDDV. VREF1
signal is the threshold level. These pins must be used as inputs in RGB
Bypass mode.
When the SYO control bit is high, the TV encoder will output a vertical
sync pulse one line wide to one of these pins. The output is driven from the
DVDD supply. This output is valid only when TV-Out is in operation.
Data Enable
These pins accept a data enable signal which is high when active video data
is input to the device, and remains low during all other times. The levels
are 0 to VDDV. VREF1 is the threshold level. The TV-Out function uses
H and V sync signals and values in the SAV register as reference to active
video.
TV Field Signal
These outputs can be programmed to be a TV Field output from the TV
encoder. These outputs are tri-stated upon power up.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and can
operate with inputs from VDDV to DVDD. Outputs are driven from 0 to
VREF2.
Serial Port Clock Input
This pin functions as the clock input of the serial port and can operate with
inputs from VDDV to DVDD.
Address Select (Internal Pull-up)
This pin determines the device address of the serial port.
Reference Voltage 2
Used to generate the output supply level for SPD port. This pin should be
tied externally to the maximum voltage seen by the ports. (1.5V to 3.3V).
General Purpose Input / Output [5:0]
These pins provide general purpose I/O and are controlled via the serial
port. (3.3V). See description of GPIO Controls for I/O configuration.
Panel Power Enable
Enable panel VDD. (3.3V)
Back Light Enable
Enable Back-Light of LCD Panel. (3.3V)
LVDS Voltage Swing Control
This pin sets the swing level of the LVDS outputs. A 2.4K Ohm resistor
should be connected between this pin and LGND (pin 35) using short and
wide traces.
Reset * Input (Internal Pull-up)
When this pin is low, the device is held in the power on reset condition.
When this pin is high, reset is controlled through the serial port.
201-0000-048
Rev. 2.4, 12/18/2006
CH7019B