ch7019 Chrontel, ch7019 Datasheet - Page 60

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
Power Sequencing T1
This register defines Power On time (T1), the time duration between LVDS_RDY (internal signal) to valid LVDS Clock
and Data. The entire bit field, TPON[8:0], is comprised of these bits TPON[7:0] plus TPON8 contained in the PST2
Power Sequencing T2 register (68h). Refer to Figure 18 and Table 15 in section 2.4.4. The range of T1 is 1ms to 512ms
in increments of 1ms.
Power Sequencing T2
TPBLE[6:0] (bits 6:0) of register PST2 define the Back Light Enable time (T2), the waiting time after valid LVDS Clock
and Data before enabling the LVDS panel back light. Refer to Figure 18 and Table 15 in section 2.4.4. The range of T2
is 2ms to 256ms in increments of 2ms.
TPON8 (bit 7) of register PST2 defines the MSB of the Power On time (T1). The entire bit field, TPON[8:0], is
comprised of this bit, TPON8, plus TPON[7:0] contained in the Power Sequencing T1 register (address 67h). Refer to
the description of the PST1 register (address 67h) for more information.
Power Sequencing T3
TPBLD[6:0] (bits 6-0) of register PST3 define the Back Light Disable time (T3), the required time after disabling the
back light before the valid LVDS Clock and Data become tri-stated or disabled. Refer to Figure 18 and Table 15 in
section 2.4.4. The range of T3 is 2ms to 256ms in increments of 2ms.
TPOFF8 (bit 7) of register PST3 defines the MSB of the Power Off time (T4). The entire bit field, TPOFF[8:0], is
comprised of this bit, TPOFF8, plus TPOFF[7:0] contained in the Power Sequencing T4 register (address 6Ah). Refer to
the description of the PST4 register (address 6Ah) for more information.
60
DEFAULT:
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
TYPE:
BIT:
BIT:
BIT:
7
7
TP0FF8 TPBLD6 TPBLD5 TPBLD4 TPBLD3 TPBLD2 TPBLD1 TPBLD0
TPON7
TPON8
R/W
R/W
R/W
0
0
0
7
6
6
TPBLE6
TPON6
R/W
R/W
R/W
0
0
6
0
5
5
TPBLE5 TPBLE4 TPBLE3 TPBLE2 TPBLE1
TPON5
R/W
R/W
R/W
0
0
5
0
4
4
TPON4
R/W
R/W
R/W
0
0
4
0
3
3
TPON3
R/W
R/W
R/W
0
0
3
0
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
201-0000-048
2
2
TPON2
R/W
R/W
R/W
0
0
0
2
1
1
TPON1
R/W
R/W
R/W
PST1
67h
8
PST2
68h
8
PST3
69h
8
Rev. 2.4, 12/18/2006
0
0
1
0
CH7019B
0
0
TPBLE0
TPON0
R/W
R/W
R/W
0
0
0
0