ch7019 Chrontel, ch7019 Datasheet - Page 27

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
2.4.3
The dither engine in the CH7019 converts 24-bit per pixel to 18-bit per pixel RGB data before sending to the LVDS
encoder. The 1D or the 2D dither algorithm can be selected via serial port programming. Maximum pixel rate supported
is 165 M Pixels / sec. This function must be bypassed when pixel rate exceeds 165MHz.
2.4.4
The CH7019 conforms to SPWG’s requirements on power sequencing. The timing specification shown in Figure 18 is a
superset of the requirements dictated by the SPWG specification. The power sequencing block consists of a state
machine and 5 hardware timers, which are programmable through serial port to suit requirements by different panels. It
provides 2 signals ENAVDD and ENABKL to the LCD panel.
Power-on sequence begins when the LVDS software registers are set properly via serial port and the internal PLL lock
detection circuit and the internal Sync detection circuits (see section 2.4.5) indicate that HSYNC, VSYNC and XCLK
are stable. Note that the BKLEN bit (register 66h) must be set in order for the ENABKL signal to be asserted. Power-off
sequence begins when any detection circuits indicate an instability in the timing signals (see section 2.4.5), or through
software programming. Once power-off sequence starts, the internal state machine will complete the sequence and
power-on sequence is allowed only after T5 is passed.
When the LVDS output clock and data signals become invalid, these outputs are tri-stated or grounded depending on the
value of the LODP bit.
2.4.5
The LCD panel can be damaged if HSYNC is absent from the LVDS link. This situation can happen when there is a
catastrophic failure in the PC or the graphics system. The CH7019 is designed to prevent damage to the panel under such
a failure. If the system fails, the CH7019 does not expect any software instruction from the graphics controller to power
down the panel. Detection circuits are used to monitor the three timing signals – HSYNC, VSYNC and XCLK. If any
one, combination of, or all of these signals becomes unstable, the CH7019 will commence Power Down Sequencing
according to section 2.4.4. A description of these detection circuits is shown in Figure 19.
201-0000-048
Table 15: Power Sequencing
Dithering
Power Sequencing
Panel Protection
LVDS Clocks
T1
T2
T3
T4
T5
LVDS_RDY
Rev. 2.4,
LVDS Data
ENEXBUF
ENAVDD
(Internal)
ENABKL
12/18/2006
T1
T2
Figure 18: Power Sequencing
Valid Clock
0-1600 ms
Valid Data
1-512 ms
2-256 ms
2-256 ms
1-512 ms
Range
T3
T4
Tristate or GND
Tristate or GND
T5
Increment
50ms
1 ms
1 ms
2ms
2ms
CH7019B
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