ch7019 Chrontel, ch7019 Datasheet - Page 7

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
2.0 Overview
The CH7019 is a VGA to TV encoder with dual LVDS output for the graphics subsystem. Both TV-Out and LVDS-Out
can operate simultaneously if the two 12-bit input ports are driven from different timing generators. TV timing
requirements are usually different from that of the TFT-LCD panels. If the graphic controller can generate only one set
of timing, simultaneous display on both the TV and the flat panel may not be available for all graphic modes.
Descriptions of each of the operating modes with block diagrams of the data flow within the device are shown below.
The CH7019 also supports 24-bit input mode by ganging D1 and D2 together as a single 24-bit data port. In this case the
timing signals H1, V1, DE1, XCLK1 and XCLK1* are equal to H2, V2, DE2, XCLK2 and XCL2* , respectively.
Video data are sent to either the TV encoder (including RGB bypass) or to the LVDS data path, but not both. Maximum
data rate supported through the dual LVDS links is 330M Pixels /sec. The maximum pixel rate supported by the RGB
bypass mode is 165 Mpixels/sec.
2.1
Four distinct methods of transferring data to the CH7019 are described below. In each of the four modes, DEx is used to
signal active LVDS data for the panel and register SAV value denotes the start of active TV video.
A. 12-bit Multiplexed Data – Dual-edge Transfer
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B. 12-bit Multiplexed Data – Single-edge Transfer
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201-0000-048
X C L K x
X C L K x *
D x [ 1 1 : 0 ]
D E x
H x
V x
Multiplexed data - two 12-bit words per pixel from either D1[11:0] or D2[11:0]
Clock frequency equals 1X pixel rate with 12-bit data transfer at both rising and falling clock edges.
Maximum pixel rate is 165M pixels per second with a 165 MHz pixel clock.
Simultaneous TV and panel display.
Multiplexed data - two 12-bit words per pixel from either D1[11:0] or D2[11:0]
Clock frequency equals 2X pixel rate with 12-bit data transfer at either rising or falling edge of clock
(programmable via serial port).
Maximum pixel rate is 165M pixels per second with a 330 MHz pixel clock.
Simultaneous TV and panel display.
Input Interface Timing
Rev. 2.4,
Figure 3: Interface Timing for Multiplexed Data – Dual-edge Transfer
12/18/2006
t
S
> = 1 V G A L i n e
6 4 P - O U T
t
H
S A V
t
S
t
H
CH7019B
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