ch7019 Chrontel, ch7019 Datasheet - Page 53

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
IDF13 (bit 5) of register DC is the MSB of the IDF1 word which is described in the IDF (address 1Fh) register
description.
XOSC[1:0] (bits 7-6) of register DC control the crystal oscillator. The entire bit field, XOSC[2:0], is comprised of
XOSC[1:0] from this register plus XOSC2 contained in the Connection Detect register (20h, bit 6).The default value is
recommended.
Buffered Clock Output Register
BCO[2:0] (bits 2-0) of register BCO select the signal output at the BCO pin, according to Table 30 below:
BCOP (bit 3) of register BCO selects the polarity of the BCO output. A value of ‘1’ does not invert the signal at the
output pad.
BCOEN (bit 4) of register BCO enables the BCO output pin. When BCOEN is high, the BCO pin will output the
selected signal. When BCOEN is low, the BCO pin will be held in tri-state mode.
Pedestal Enable
PEDLEN (bit 0) of register PEN enables the pedestal (in register 4Fh). When PEDLEN is ‘0’ the pedestal function is
disabled. When PEDLEN is ‘1’ the pedestal is enabled.
201-0000-048
DEFAULT:
DEFAULT:
SYMBOL:
Table 30: BCO Output Signal
SYMBOL:
SYNCO[1:0]
Table 29: Composite / Horizontal Sync Output
BCO[2:0]
000
001
010
011
TYPE:
TYPE:
00
01
10
11
BIT:
BIT:
Reserved Reserved Reserved
Reserved
R/W
R/W
The 14MHz crystal
Field ID
Buffered Clock Output
Rev. 2.4,
7
0
7
0
Composite / Horizontal Sync Output
No Output
VGA Horizontal Sync
TV Composite Sync
TV Horizontal Sync
Reserved Reserved Reserved Reserved Reserved Reserved
R/W
R/W
12/18/2006
6
0
6
0
R/W
R/W
5
0
5
0
BCOEN
R/W
R/W
4
0
4
0
BCO[2:0]
100
101
110
111
BCOP
R/W
R/W
3
0
3
0
Sine ROM MSB
Cosine ROM MSB
VGA Vertical Sync
TV Vertical Sync
Buffered Clock Output
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
BCO2
R/W
R/W
2
0
2
0
BCO1
R/W
R/W
BCO
22h
5
PEN
23h
1
1
0
1
0
CH7019B
PEDLEN
BCO0
R/W
R/W
0
0
0
0
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