DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet
DAC1408D650C1
Related parts for DAC1408D650C1
DAC1408D650C1 Summary of contents
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DAC1408D650 Dual 14-bit DAC 650 Msps; 2×, 4× or 8× interpolating Rev. 02 — 11 August 2010 1. General description The DAC1408D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2×, 4× or 8× interpolating ...
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NXP Semiconductors Two’s complement or binary offset data format LMF = 421 or LMF = 211 support Differential CML receiver with embedded termination Synchronization of multiple DAC devices outputs 3. Applications Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication: ...
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Block diagram SDO SDIO SPI CONTROL REGISTERS SYNC_OUTP DIGITAL LAYER PROCESSING SYNC_OUTN JESD204A VIN_P0 LANE L0 PROC VIN_N0 VIN_P1 LANE L1 PROC VIN_N1 VIN_P2 LANE L2 PROC VIN_N2 VIN_P3 LANE L3 PROC VIN_N3 CLOCK GENERATOR UNIT CLK_INP CLK_INN Fig ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Symbol SDO SDIO SCLK V DDD(1V8) SCS_N RESET_N n.c. VIRES GAPOUT V DDA(1V8) V DDA(1V8) DAC1408D650 Preliminary data sheet DAC1408D 650 Msps; 2×, 4× ...
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NXP Semiconductors Table 2. Symbol AGND AUXBN AUXBP V DDA(3V3) AGND V DDA(1V8) AGND V DDA(1V8) V DDA(1V8) AGND IOUTBN IOUTBP AGND AGND IOUTAP IOUTAN AGND V DDA(1V8) V DDA(1V8) AGND V DDA(1V8) AGND V DDA(3V3) AUXAP AUXAN AGND V ...
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NXP Semiconductors Table 2. Symbol VIN_N0 VIN_P0 V DDD(1V8) VIN_P1 VIN_N1 VIN_N2 VIN_P2 V DDD(1V8) VIN_P3 VIN_N3 n.c. n.c. JTAG GND [1] P: power supply; G: ground; I: input; O: output. [ heatsink (exposed die pad to be ...
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NXP Semiconductors 9. Characteristics Table 5. Characteristics 1 1 DDA(1V8) DDD typical values measured at V DDA(1V8) sample rate; PLL off unless otherwise specified. Symbol Parameter V analog supply voltage DDA(3V3) (3.3 ...
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NXP Semiconductors Table 5. Characteristics …continued 1 1 DDA(1V8) DDD typical values measured at V DDA(1V8) sample rate; PLL off unless otherwise specified. Symbol Parameter V HIGH-level input IH voltage I LOW-level ...
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NXP Semiconductors Table 5. Characteristics …continued 1 1 DDA(1V8) DDD typical values measured at V DDA(1V8) sample rate; PLL off unless otherwise specified. Symbol Parameter Reference voltage output (GAPOUT) V reference output ...
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NXP Semiconductors Table 5. Characteristics …continued 1 1 DDA(1V8) DDD typical values measured at V DDA(1V8) sample rate; PLL off unless otherwise specified. Symbol Parameter SFDR restricted bandwidth RBW spurious-free dynamic range ...
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NXP Semiconductors 10. Application information 10.1 General description The DAC1408D650 is a dual 14-bit DAC operating up to 650 Msps. With a maximum input data rate 312.5 Msps and a maximum output sampling rate of 650 Msps, ...
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NXP Semiconductors 10.2 JESD204A receiver SYNC_OUT 10b CLOCK lane# DES ALIGN frame clock The descrambler can be enabled/disabled Fig 3. JESD204A receiver The JEDEC204A defines the following parameters: The DAC1408D650 supports both LMF = 421 and LMF = 211. The ...
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NXP Semiconductors 10.2.1 Lane input Each lane is CML compliant terminated to a common voltage with an integrated 50 Ω resistor. Fig 4. The common mode voltage is programmable. See value. DC coupling is only possible if both ...
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NXP Semiconductors The lane processing makes use of the SYNC-patterns to synchronize the datastream, determine the initial running disparity and extract the 10-bit word from the incoming datastream (word-alignment). The SYNC signal is also used during normal operation by the ...
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NXP Semiconductors A flag is sent to the control interface to reflect detected commas in registers. The following flags are also triggered according to the following definitions: • VALID: a code group that is found in the column of the ...
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NXP Semiconductors • if the buffers are empty or overflow, this will be indicated by the registers buff_err_ln0 to buff_err_ln3 10.2.5.2 Multi-device operation DAC1408D650 implements a multi-device interlane alignment that guarantees a skew of less than one output period between ...
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NXP Semiconductors 10.2.5.3 Master/slave mode The external reference is provided by one of the DACs (the master DAC), which has to be configured to be able to do this. The others are set to Slave mode. TX Fig 9. DAC1408D650 ...
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NXP Semiconductors The MDS signal generated by the master DAC must reach all slaves within one DAC output clock period. This induces PCB layout constraints for the MDS signal and also for the clock distribution. Because trace lengths differ, the ...
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NXP Semiconductors Fig 11. Clock skew case 2: Master is closest The worst case clock skew is given by The minimum allowable trace delay for the MDS signal is given by In real applications, the master DAC can be anywhere ...
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NXP Semiconductors 10.2.5.4 All slave mode The external reference is provided by the JESD204A transmitter. All DACs are configured in Slave mode. INSERTION Fig 12. All slave mode The MDS signal is now driven from the transmitter generated ...
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NXP Semiconductors 10.2.6 Frame assembly DAC1408D650 supports only / which means that every frame clock period carries one byte per lane. Frame assembly combines the octet of lane_0 with the six MSB bits of lane_1 and reassemble the ...
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NXP Semiconductors SERIAL CLOCK 3.125 GHz Fig 13. ...
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NXP Semiconductors 10.3 Serial Peripheral Interface (SPI) 10.3.1 Protocol description The DAC1408D650 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the ...
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NXP Semiconductors 10.3.2 SPI timing description The SPI interface can operate at a frequency MHz. The SPI timing is shown in Figure 15. RESET_N SCS_N Fig 15. SPI timing diagram The SPI timing characteristics are given ...
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NXP Semiconductors 10.4 Clock input The DAC1408D650 has one differential clock input, CLKINN/CLKINP. Fig 16. LVDS clock configuration Fig 17. Interfacing CML to LVDS The DAC1408D650 can operate with a clock frequency up to 312.5 MHz 650 ...
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NXP Semiconductors 10.5 FIR filters The three interpolation FIR filters have a stop band attenuation of at least 80 dBc and a pass band ripple of less than 0,0005 dB. Table 11. First interpolation filter Lower H(1) H(2) H(3) H(4) ...
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NXP Semiconductors 10.6 Quadrature modulator and Numerically Controlled Oscillator (NCO) The quadrature modulator allows the 14-bit I and Q data to be mixed with the carrier signal generated by the NCO. The frequency of the NCO is programmed over 32 ...
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NXP Semiconductors Table 12. First interpolation filter Lower H(1) H(2) H(3) H(4) H(5) 10.8 DAC transfer function The full scale output current for each DAC is the sum of the two complementary current outputs ...
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NXP Semiconductors 10.9 Full scale current 10.9.1 Regulation The DAC1408D650 reference circuitry integrates an internal bandgap reference voltage which delivers a 1.25 V reference to the GAPOUT pin recommended to decouple pin GAPOUT using a 100 nF capacitor. ...
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NXP Semiconductors Table 14. Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] Decimal The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see “DAC_A_CFG_2 register (address 0Ah) bit ...
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NXP Semiconductors (register 0Ch; see register 0Eh; see the range of variation of the digital offset (see Table 16. Default settings are shown highlighted. DAC_OFFSET[11:0] Decimal −2048 −2047 ... − ... +2046 +2047 10.11 Analog output The DAC1408D650 ...
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NXP Semiconductors 10.12 Auxiliary DACs The DAC1408D650 integrates two auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a 10-bit resolution and are ...
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NXP Semiconductors 10.13 Output configuration 10.13.1 Basic output configuration The use of a differentially-coupled transformer output provides optimum distortion performance (see electrical isolation. Fig 20 The DAC1408D650 can operate recommended to connect the ...
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NXP Semiconductors 10.13.2 DC interface to an Analog Quadrature Modulator (AQM) When the system operation requires to keep the DC component of the spectrum, the DAC1408D650 can use a DC interface to connect to an AQM. In this case, the ...
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NXP Semiconductors Fig 24. An example interface to a 1.7 V Figure 25 a 3.3 V Fig 25. An example interface to a 3.3 V The constraints to adjust the interface are the output ...
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NXP Semiconductors 10.13.3 AC interface to an Analog Quadrature Modulator (AQM) When the AQM common mode voltage is close to ground, the DAC1408D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 26 input level when ...
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NXP Semiconductors 10.13.4 Phase correction The Analog Quadrature Modulator which follows the DACs may have a phase imbalance which will result in undesired sideband. By adjusting the phase between the I and Q channels, the spur can be reduced. Without ...
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Page 0 allocation map description Table 18. Page 0 register allocation map Address Register name R/W Bit definition b7 0 00h COMMON R/W SPI_3W 1 01h TXCFG R/W NCO_EN 2 02h PLLCFG R/W PD_PLL 3 03h FREQNCO_LSB R/W 4 ...
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Table 18. Page 0 register allocation map …continued Address Register name R/W Bit definition b7 27 1Bh DAC_A_AUX_LSB R/W DAC_A_AUX_ PD 28 1Ch DAC_B_AUX_MSB R/W 29 1Dh DAC_B_AUX_LSB R/W DAC_B_AUX_ PD 31 1Fh PAGE_ADDRESS R ...
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NXP Semiconductors 10.15.2.2 Page 0 bit definition detailed description Please refer to values emphasized in bold are the default values. Table 19. COMMON register (address 00h) bit description Default settings are shown highlighted. Bit Symbol 7 SPI_3W 6 SPI_RST 2 ...
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NXP Semiconductors Table 20. TXCFG register (address 01h) bit description Default settings are shown highlighted. Bit Symbol INT_FIR[1:0] Table 21. PLLCFG register (address 02h) bit description Default settings are shown highlighted. Bit Symbol 7 PLL_PD 6 - ...
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NXP Semiconductors Table 25. FREQNCO_MSB register (address 06h) bit description Bit Symbol FREQ_NCO[31:24] Table 26. PHINCO_LSB register (address 07h) bit description Bit Symbol PH_NCO[7:0] Table 27. PHINCO_MSB register (address 08h) bit description Bit Symbol ...
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NXP Semiconductors Table 31. DAC_B_CFG_1 register (address 0Ch) bit description Default settings are shown highlighted. Bit Symbol 7 DAC_B_PD 6 DAC_B_SLEEP DAC_B_OFFSET[5:0] Table 32. DAC_B_CFG_2 register (address 0Dh) bit description Bit Symbol DAC_B_GAIN_COARSE[1:0] 5 ...
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NXP Semiconductors Table 37. DAC_CURRENT_2 register (address 13h) bit description Default settings are shown highlighted. Bit Symbol DAC_DRV_BIAS[2: DAC_SLV_BIAS[2:0] Table 38. DAC_CURRENT_3 register (address 14h) bit description Default settings are shown highlighted. Bit Symbol ...
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NXP Semiconductors Table 45. DAC_B_AUX_LSB register (address 1Dh) bit description Default settings are shown highlighted. Bit Symbol 7 AUX_B_PD AUX_B[1:0] Table 46. DAC_B_AUX_LSB register (address 1Dh) bit description Default settings are shown highlighted. Bit Symbol 2 to ...
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Page 1 allocation map description Table 48. Page 1 register allocation map Address Register name R/W Bit definition b7 0 00h MDS_MAIN R/W MDS_EQCHECK[1:0] 1 01h MDS_WIN_PERIOD_A R/W 2 02h MDS_WIN_PERIOD_B R/W 3 03h MDS_MISCCNTRL0 R 04h ...
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NXP Semiconductors 10.15.2.4 Page 1 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 49. MDS_MAIN register (address 00h) bit description Default settings are shown highlighted. Bit Symbol 7 to ...
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NXP Semiconductors Table 52. MDS_MISCCNTRL0 register (address 03h) bit description Default settings are shown highlighted. Bit Symbol 4 MDS_EVAL_ENA 3 MDS_PRERUN_ENA MDS_PULSEWIDTH[2:0] Table 53. MDS_MAN_ADJUSTDLY register (address 04h) bit description Default settings are shown highlighted. Bit Symbol ...
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NXP Semiconductors Table 55. MDS_MISCCNTRL1 register (address 06h) bit description Default settings are shown highlighted. Bit Symbol 4 MDS_RELOCK MDS_LOCK_DELAY[3:0] Table 56. MDS_ADJDELAY register (address 08h) bit description Default settings are shown highlighted. Bit Symbol 6 to ...
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NXP Semiconductors Table 58. MDS_STATUS1 register (address 0Ah) bit description Default settings are shown highlighted. Bit Symbol 3 JD_ODD 2 MDS_PRERUN 1 MDS_LOCKOUT 0 MDS_LOCK Table 59. PAGE_ADDRESS register (address 1Fh) bit description Default settings are shown highlighted. Bit Symbol ...
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Page 2 allocation map description Table 60. Page 2 register allocation map Address Register name R/W Bit definition b7 0 00h MAINCONTROL R 03h JCLK_CNTRL R/W SR_CDI 4 04h RST_EXT_FCLK R/W 5 05h RST_EXT_DCLK R/W 6 06h ...
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NXP Semiconductors 10.15.2.6 Page 2 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 61. MAINCONTROL register (address 00h) bit description Default settings are shown highlighted. Bit Symbol 5 FULL_RE_INIT ...
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NXP Semiconductors Table 63. RST_EXT_FCLK register (address 04h) bit description Default settings are shown highlighted. Bit Symbol RST_EXT_FCLK[7:0] Table 64. RST_EXT_DCLK register (address 05h) bit description Default settings are shown highlighted. Bit Symbol RST_EXT_DCLK[7:0] ...
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NXP Semiconductors Table 71. TYPE_ID register (address 1Bh) bit description Default settings are shown highlighted. Bit Symbol 7 DAC FRONTEND [1:0] 4 DUAL DSP BIT_RES[1:0] Table 72. DAC_VERSION register (address 1Ch) ...
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NXP Semiconductors Table 76. Register 16h: SET_VCM_VOLTAGE Dec Table 77. Register 17h: SET_SYNC Dec Table 78. ...
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Page 4 allocation map description Table 79. Page 4 register allocation map Address Register name R/W Bit definition 00h SR_DLP_0 R/W SR_SWA_ SR_SWA_ LN3 1 01h SR_DLP_1 R/W SR_CNTRL SR_CNTRL _LN3 2 02h FORCE_LOCK R/W FORCE_ ...
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Table 79. Page 4 register allocation map …continued Address Register name R/W Bit definition 12h INIT_SCR_ R/W - S7T1_LN0 19 13h INIT_SCR_ R/W S15T8_LN1 20 14h INIT_SCR_ R/W - S7T1_LN1 21 15h INIT_SCR_ R/W S15T8_LN2 22 16h ...
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NXP Semiconductors 10.15.2.8 Page 4 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 80. SR_DLP_0 register (address 00h) bit description Default settings are shown highlighted. Bit Symbol 7 SR_SWA_LN3 ...
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NXP Semiconductors Table 82. FORCE_LOCK register (address 02h) bit description Default settings are shown highlighted. Bit Symbol 0 SR_ILA Table 83. MAN_LOCK_LN_1_0 register (address 03h) bit description Default settings are shown highlighted. Bit Symbol MAN_LOCK_LN1[3: ...
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NXP Semiconductors Table 85. CA_CNTRL register (address 05h) bit description Bit Symbol 1 SELECT_RF_F10_LN1 0 SELECT_RF_F10_LN0 Table 86. SCR-CNTRL register (address 06h) bit description Bit Symbol 7 MAN_SCR_LN3 6 MAN_SCR_LN2 5 MAN_SCR_LN1 4 MAN_SCR_LN0 3 FORCE_SRC_LN3 2 FORCE_SRC_LN2 1 FORCE_SRC_LN1 ...
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NXP Semiconductors Table 87. ILA_CNTRL register (address 07h) bit description Bit Symbol 7 SEL_421_211 SEL_ILA[1: SEL_LOCK[2:0] 1 SUP_LANE_SYN 0 EN_SCR Table 88. FORCE_ALIGN register (address 08h) bit description Bit Symbol 1 DYN_ALIGN_ENA 0 FORCE_ALIGN ...
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NXP Semiconductors Table 90. MAN_ALIGN_LN_2_3 register (address 0Ah) bit description Bit Symbol MAN_ALIGN_LN3[3: MAN_ALIGN_LN2[3:0] Table 91. FA_ERR_HANDLING register (address 0Bh) bit description Default settings are shown highlighted. Bit Symbol SEL_KOUT_ UNEXP_LN23[1:0] ...
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NXP Semiconductors Table 92. SYNCOUT_MODE register (address 0Ch) bit description Default settings are shown highlighted. Bit Symbol SEL_RE_INIT[2:0] 4 SYNC_POL SEL_SYNC[3:0] Table 93. LANE_POLARITY register (address 0Dh) bit description Bit Symbol 3 POL_LN3 2 ...
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NXP Semiconductors Table 94. LANE_SELECT register (address 0Eh) bit description Default settings are shown highlighted. Bit Symbol LANE_SEL_LN3[1: LANE_SEL_LN2[1: LANE_SEL_LN1[1: LANE_SEL_LN0[1:0] Table 95. SOFT_RESET_SCRAMBLER register (address 10h) bit ...
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NXP Semiconductors Table 97. INIT_SCR_S7T1_LN0 (address 12h) bit description Bit Symbol INIT_VALUE_S7_S1_LN0[6:0] Table 98. INIT_SCR_S15T8_LN1 register (address 13h) bit description Bit Symbol INIT_VALUE_S15_S8_LN1[7:0] Table 99. INIT_SCR_S7T1_LN1 register (address 14h) bit description Bit Symbol 6 ...
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NXP Semiconductors Table 106. ERROR_HANDLING register (address 1Bh) bit description Default settings are shown highlighted. Bit Symbol 6 NAD_ERR_CORR 5 KUX_CORR 4 NAD_CORR CORR_MODE[1:0] 1 IMPL_ALT 0 IGNORE_ERR Table 107. REINIT_CNTRL register (address 1Ch) bit description Default ...
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NXP Semiconductors Table 107. REINIT_CNTRL register (address 1Ch) bit description Default settings are shown highlighted. Bit Symbol 3 RESYNC_O_L_LN3 2 RESYNC_O_L_LN2 1 RESYNC_O_L_LN1 0 RESYNC_O_L_LN0 Table 108. PAGE_ADDRESS register (address 1Fh) bit description Bit Symbol PAGE[2:0] DAC1408D650 ...
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Page 5 allocation map description Table 109. Page 5 register allocation map Address Register name R/W Bit definition 00h ILA_MON_1_0 R 1 01h ILA_MON_3_2 R 2 02h ILA_BUF_ERR 03h CA_MON R CA_MON_LN3[1:0] 4 ...
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Table 109. Page 5 register allocation map …continued Address Register name R/W Bit definition 11h FLAG_CNT_ R MSB_LN0 18 12h FLAG_CNT_LSB R _LN1 19 13h FLAG_CNT_ R MSB_LN1 20 14h FLAG_CNT_LSB R _LN2 21 15h FLAG_CNT_ R ...
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NXP Semiconductors 10.15.2.10 Page 5 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 110. ILA_MON_1_0 register (address 00h) bit description Default settings are shown highlighted. Bit Symbol 7 to ...
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NXP Semiconductors Table 114. DEC_FLAGS register (address 04h) bit description Bit Symbol 7 DEC_NIT_ERR_LN3 6 DEC_NIT_ERR_LN2 5 DEC_NIT_ERR_LN1 4 DEC_NIT_ERR_LN0 3 DEC_DISP_ERR_LN3 2 DEC_DISP_ERR_LN2 1 DEC_DISP_ERR_LN1 0 DEC_DISP_ERR_LN0 Table 115. KOUT_FLAG register (address 05h) bit description Bit Symbol 3 DEC_KOUT_LN3 ...
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NXP Semiconductors Table 119. K28_LN3_FLAG register (address 09h) bit description Bit Symbol 4 K28_7_LN3 3 K28_5_LN3 2 K28_4_LN3 1 K28_3_LN3 0 K28_0_LN3 Table 120. KOUT_UNEXPECTED_FLAG register (address 0Ah) bit description Bit Symbol 3 DEC_KOUT_UNEXP_LN3 2 DEC_KOUT_UNEXP_LN2 1 DEC_KOUT_UNEXP_LN1 0 DEC_KOUT_UNEXP_LN0 ...
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NXP Semiconductors Table 125. INTR_MISC_ENA register (address 0Fh) bit description Default settings are shown highlighted. Bit Symbol 7 INTR_ENA_CS_INIT_LN3 6 INTR_ENA_CS_INIT_LN2 5 INTR_ENA_CS_INIT_LN1 4 INTR_ENA_CS_INIT_LN0 3 INTR_ENA_BUF_ERR_LN3 2 INTR_ENA_BUF_ERR_LN2 1 INTR_ENA_BUF_ERR_LN1 0 INTR_ENA_BUF_ERR_LN0 Table 126. FLAG_CNT_LSB_LN0 register (address 10h) bit ...
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NXP Semiconductors Table 133. FLAG_CNT_MSB_LN3 register (address 17h) bit description Default settings are shown highlighted. Bit Symbol FLAG_CNT_LN3[15:8] Table 134. BER_LEVEL_LSB register (address 18h) bit description Default settings are shown highlighted. Bit Symbol BER_LEVEL[7:0] ...
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NXP Semiconductors Table 137. CNTRL_FLAGCNT_LN01 register (address 1Bh) bit description Default settings are shown highlighted. Bit Symbol 7 RST_CFC_LN1 SEL_CFC_LN1[2:0] 3 RST_CFC_LN0 SEL_CFC_LN0[2:0] Table 138. CNTRL_FLAGCNT_LN23 register (address 1Ch) bit description Default settings are ...
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NXP Semiconductors Table 140. DBG_CNTRL register (address 1Eh) bit description Bit Symbol 7 BER_MODE 6 INTR_CLEAR INTR_MODE[2:0] Table 141. PAGE_ADDRESS register (address 1Fh) bit description Bit Symbol PAGE[2:0] Table 142. Counter source Default settings ...
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Page 6 allocation map description Table 143. Page 6 register allocation map Address Register name R/W Bit definition b7 0 00h LN0_CFG_0 R 1 01h LN0_CFG_1 02h LN0_CFG_2 03h LN0_CFG_3 R LN0_SCR 4 ...
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Table 143. Page 6 register allocation map …continued Address Register name R/W Bit definition b7 28 1Ch LN1_CFG_12 R 29 1Dh LN1_CFG_13 R 31 1Fh PAGE_ADDRESS R undefined at power-up or after reset ...
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NXP Semiconductors 10.15.2.12 Page 6 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 144. LN0_CFG_0 register (address 00h) bit description Default settings are shown highlighted. Bit Symbol 7 to ...
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NXP Semiconductors Table 152. LN0_CFG_8 register (address 08h) bit description Default settings are shown highlighted. Bit Symbol LN0_N’[4:0] Table 153. LN0_CFG_9 register (address 09h) bit description Default settings are shown highlighted. Bit Symbol LN0_S[4:0] ...
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NXP Semiconductors Table 161. LN1_CFG_3 register (address 13h) bit description Default settings are shown highlighted. Bit Symbol 7 LN1_SCR LN1_L[4:0] Table 162. LN1_CFG_4 register (address 14h) bit description Default settings are shown highlighted. Bit Symbol 7 to ...
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NXP Semiconductors Table 170. LN1_CFG_12 register (address 1Ch) bit description Default settings are shown highlighted. Bit Symbol LN1_RES2[7:0] Table 171. LN1_CFG_13 register (address 1Dh) bit description Default settings are shown highlighted. Bit Symbol LN1_FCHK[7:0] ...
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Page 7 allocation map description Table 173. Page 7 register allocation map Address Register name R/W Bit definition b7 0 00h LN2_CFG_0 R 1 01h LN2_CFG_1 02h LN2_CFG_2 03h LN2_CFG_3 R LN2_SCR 4 ...
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Table 173. Page 7 register allocation map …continued Address Register name R/W Bit definition b7 28 1Ch LN3_CFG_12 R 29 1Dh LN3_CFG_13 R 31 1Fh PAGE_ADDRESS R undefined at power-up or after reset ...
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NXP Semiconductors 10.15.2.14 Page 7 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 174. LN2_CFG_0 register (address 00h) bit description Default settings are shown highlighted. Bit Symbol 7 to ...
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NXP Semiconductors Table 182. LN2_CFG_8 register (address 08h) bit description Default settings are shown highlighted. Bit Symbol LN2_N'[4:0] Table 183. LN2_CFG_9 register (address 09h) bit description Default settings are shown highlighted. Bit Symbol LN2_S[4:0] ...
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NXP Semiconductors Table 191. LN3_CFG_3 register (address 13h) bit description Default settings are shown highlighted. Bit Symbol 7 LN3_SCR LN3_L[4:0] Table 192. LN3_CFG_4 register (address 14h) bit description Default settings are shown highlighted. Bit Symbol 7 to ...
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NXP Semiconductors Table 200. LN3_CFG_12 register (address 1Ch) bit description Default settings are shown highlighted. Bit Symbol LN3_RES2[7:0] Table 201. LN3_CFG_13 register (address 1Dh) bit description Default settings are shown highlighted. Bit Symbol LN3_FCHK[7:0] ...
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NXP Semiconductors 11. Package outline HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 0.85 mm terminal 1 index area terminal 1 64 index area ...
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NXP Semiconductors 12. Abbreviations Table 203. Abbreviations Acronym AQM BW BWA CDMA CML CMOS DAC EDGE FIR GSM IF IMD3 LMDS LTE LVDS NCO NMOS PLL SERDES SFDR SPI TD-SCDMA WCDMA WiMax WLL DAC1408D650 Preliminary data sheet DAC1408D ...
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NXP Semiconductors 13. Revision history Table 204. Revision history Document ID Release date DAC1408D650 v.2 20100811 • Modifications: Template upgraded to Rev 2.12.0 including revised legal information. • Text and drawings updated throughout entire data sheet. DAC1408D650_1 20090526 DAC1408D650 Preliminary ...
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NXP Semiconductors 14. Legal information 14.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use neither qualified nor tested in accordance with automotive testing ...
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NXP Semiconductors 16. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . ...
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NXP Semiconductors Table 59. PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 60. Page 2 register ...
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NXP Semiconductors Table 113. CA_MON register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .70 Table 114. DEC_FLAGS register (address ...
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NXP Semiconductors Table 165. LN1_CFG_7 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 166. LN1_CFG_8 register (address ...
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NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . ...