DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 19

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650
Preliminary data sheet
The worst case clock skew is given by
The minimum allowable trace delay for the MDS signal is given by
In real applications, the master DAC can be anywhere and both conditions must be
satisfied:
Example:
⇒ 200 ps + 80 ps < Δt
⇒ 280 ps < Δt
⇒ 4.2 cm < L
Fig 11. Clock skew case 2: Master is closest
•
•
•
•
clock generator skew = ± 80 ps
FR4 substrate ⇒ 15 cm/ns delay
clock trace length difference = 3 cm and 4 cm
Output sampling rate = 650 Msps
δt
2
<
mds
slave 1 clock
slave 2 clock
master clock
mds
Δt
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
ref clock
mds
< 17.8 cm
< 1192 ps
<
mds
Rev. 02 — 11 August 2010
TDAC δt
< 1538 ps − (266 ps + 80 ps)
–
1
.
PH01
PH02
δt
PH03
2
TDAC
=
PH03 PH01
–
DAC1408D650
.
Δt
001aal071
=
© NXP B.V. 2010. All rights reserved.
δt
2
.
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