DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 49

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DAC1408D650C1

Manufacturer Part Number
DAC1408D650C1
Description
Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
Table 55.
Default settings are shown highlighted.
Table 56.
Default settings are shown highlighted.
Table 57.
Default settings are shown highlighted.
DAC1408D650
Preliminary data sheet
Bit
4
3 to 0
Bit
6 to 0
Bit
7
6
5
4
3
2
1
0
Symbol
MDS_RELOCK
MDS_LOCK_DELAY[3:0]
Symbol
MDS_ADJDELAY[6:0]
Symbol
EARLY
LATE
EQUAL
MDS_LOCK
EARLY_ERROR
LATE_ERROR
EQUAL_FOUND
MDS_ACTIVE
MDS_MISCCNTRL1 register (address 06h) bit description
MDS_ADJDELAY register (address 08h) bit description
MDS_STATUS0 register (address 09h) bit description
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
Access
R/W
R/W
Access
R
Access
R
R
R
R
R
R
R
R
Rev. 02 — 11 August 2010
Value
0
1
Fh
Value
-
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
number of succeeding 'equal'-detections until lock
Description
actual value adjustment delay
Description
early signal (sampled) from early-late detector
late signal (sampled) from early-late detector
equal signal (sampled) from early-late detector
result equal check
adjustment delay maximum value stops the search
adjustment delay minimum value stops the search
eval_logic has detected equal condition
eval_logic active
relock mode
…continued
no action
relock when lockout occurs
false
true
false
true
false
true
false
true
false
true
false
true
false
true
false
true
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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