DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 16

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650
Preliminary data sheet
10.2.5.2 Multi-device operation
DAC1408D650 implements a multi-device interlane alignment that guarantees a skew of
less than one output period between them.
Two modes are available: Master/slave and All slave. Both make use of the MDS_P and
MDS_N pins.
Each DAC device of the system generates its own reference (ref_A on
If configured as slave, an early-late comparator compares the internal reference with the
external reference provided by the MDS pins. The comparator controls an internal buffer
that is used to delay the samples.
Fig 8.
•
if the buffers are empty or overflow, this will be indicated by the registers buff_err_ln0
to buff_err_ln3
Multi-Device Synchronization (MDS) implementation
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
SYNC~
LANES
Rev. 02 — 11 August 2010
DIG
ref_A
BUFFER
MGMT
COMP
CLK
CK
mds_A_out
mds_A
DAC
Q
I
DAC1408D650
001aal073
MDS_A
© NXP B.V. 2010. All rights reserved.
Figure
8).
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