DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 59

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 82.
Default settings are shown highlighted.
Table 83.
Default settings are shown highlighted.
Table 84.
Default settings are shown highlighted.
Table 85.
DAC1408D650
Preliminary data sheet
Bit
0
Bit
7 to 4
3 to 0
Bit
7 to 4
3 to 0
Bit
7
6
5
4
3
2
Symbol
SR_ILA
Symbol
MAN_LOCK_LN1[3:0]
MAN_LOCK_LN0[3:0]
Symbol
MAN_LOCK_LN3[3:0]
MAN_LOCK_LN2[3:0]
Symbol
WORD_SWAP_LN3
WORD_SWAP_LN2
WORD_SWAP_LN1
WORD_SWAP_LN0
SELECT_RF_F10_LN3
SELECT_RF_F10_LN2
FORCE_LOCK register (address 02h) bit description
MAN_LOCK_LN_1_0 register (address 03h) bit description
MAN_LOCK_2_0 register (address 04h) bit description
CA_CNTRL register (address 05h) bit description
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
Access
R/W
Access
R/W
R/W
Access
R/W
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 02 — 11 August 2010
Value
0
1
Value
0h
0h
Value
0h
0h
Value
0
1
0
1
0
1
0
1
0
1
0
1
…continued
Description
Description
manual lock setting synchronization word alignment
lane 1
manual lock setting synchronization word alignment
lane 0
Description
manual lock setting synchronization word alignment
lane 3
manual lock setting synchronization word alignment
lane 2
Description
lane 3 bit swapping
lane 2 bit swapping
lane 1 bit swapping
lane 0 bit swapping
soft reset interlane alignment
lane 3 sampling mode
lane 2 sampling mode
no action
reset
dout_ca_ln3[7:0] = din_ca_ln3[7:0]
dout_ca_ln3[7:0] = din_ca_ln3[0:7]
dout_ca_ln2[7:0] = din_ca_ln2[7:0]
dout_ca_ln2[7:0] = din_ca_ln2[0:7]
dout_ca_ln1[7:0] = din_ca_ln1[7:0]
dout_ca_ln1[7:0] = din_ca_ln1[0:7]
dout_ca_ln0[7:0] = din_ca_ln0[7:0]
dout_ca_ln0[7:0] = din_ca_ln0[0:7]
din_ca_ln3 sampled at falling edge f10_ln3
din_ca_ln3 sampled at rising edge f10_ln3
din_ca_ln2 sampled at falling edge f10_ln2
din_ca_ln2 sampled at rising edge f10_ln2
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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