ADSP-21363SBBC-ENG AD [Analog Devices], ADSP-21363SBBC-ENG Datasheet

ADSP-21363SBBC-ENG

Manufacturer Part Number

ADSP-21363SBBC-ENG

Description

SHARC Processor

Manufacturer

AD [Analog Devices]

Datasheet

1.ADSP-21363SBBC-ENG.pdf (44 pages)

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Preliminary Technical Data

SUMMARY

High performance 32-bit/40-bit floating point processor

At 333 MHz/2 GFLOPs, with unique audio centric peripherals

Single-Instruction Multiple-Data (SIMD) computational

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

optimized for professional audio processing

such as the Digital Audio Interface the ADSP-21363 SHARC

processor is ideal for applications that require industry

leading equalization, reverberation and other effects

processing

architecture

Two 32-bit IEEE floating-point/32-bit fixed-point/40-bit

extended precision floating-point computational units,

each with a multiplier, ALU, shifter, and register file

PROCESSING

ELEMENT

(PEX)

8X4X32

DAG1

PROCESSING

CORE PROCESSOR

ELEMENT

8X4X32

DAG2

(PEY)

JTAG TEST & EMULATION

PM ADDRESS BUS

PM DATA BUS

PX REGISTER

DM ADDRESS BUS

TIMER

SEQUENCER

PROGRAM

DM DATA BUS

Figure 1. Functional Block Diagram – Processor Core

INSTRUCTION

32 X 48-BIT

CACHE

ADDR

1M BIT

SRAM

IOA

BLOCK 0

DATA

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel:781.329.4700

Fax:781.326.8703

On-chip memory—3M bit of on-chip SRAM and a dedicated

Code compatible with all other members of the SHARC family

The ADSP-21363 is available with a 333 MHz core instruction

(MEMORY MAPPED)

2M BIT

4M bit of on-chip mask-programmable ROM

rate. For complete ordering information, see

Guide on Page 44

ROM

IOD

IOP REGISTERS

ADDR

4 BLOCKS OF ON-CHIP MEMORY

1M BIT

SRAM

IOA

BLOCK 1

DATA

AND I/O INTERFACE FEATURES”

2M BIT

ROM

AND PERIPHERALS

SEE “ADSP-21363 MEMORY

IOD

I/O PROCESSOR

SECTION FOR DETAILS

ADDR

SHARC

SPORTS

TIMERS

PCG

SPI

IDP

IOA

0.5M BIT

BLOCK 2

SRAM

DATA

IOD

ADSP-21363

ADDR

Processor

BLOCK 3

0.5M BIT

IOA

SRAM

ROUTING

www.analog.com

SIGNAL

UNIT

DATA

Ordering

IOD

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