ADSP-21363SBBC-ENG AD [Analog Devices], ADSP-21363SBBC-ENG Datasheet - Page 21
ADSP-21363SBBC-ENG
Manufacturer Part Number
ADSP-21363SBBC-ENG
Description
SHARC Processor
Manufacturer
AD [Analog Devices]
Datasheet
1.ADSP-21363SBBC-ENG.pdf
(44 pages)
- Current page: 21 of 44
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Preliminary Technical Data
Timer WDTH_CAP Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in WDTH_CAP (pulse width count and capture)
mode. Timer signals are routed to the DAI_P20–1 pins through
the SRU. Therefore, the timing specifications provided below
are valid at the DAI_P20–1 pins.
Table 16. Timer Width Capture Timing
DAI Pin to Pin Direct Routing
For direct pin connections only (for example DAI_PB01_I to
DAI_PB02_O).
Table 17. DAI Pin to Pin Routing
Parameter
Timing Requirement
t
Parameter
Timing Requirement
t
PWI
DPIO
Timer Pulse Width
Delay DAI Pin Input Valid to DAI Output Valid
(TIMER2-0)
DAI_P20-1
DAI_Pm
DAI_Pn
Rev. PrA | Page 21 of 44 | September 2004
Figure 14. DAI Pin to PIN Direct Routing
Figure 13. Timer Width Capture Timing
Min
2 t
PCLK
t
DPIO
t
PWI
Min
1.5
Max
2(2
31
– 1) t
PCLK
Max
10
ADSP-21363
Unit
ns
Unit
ns
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