ADSP-21363SBBC-ENG AD [Analog Devices], ADSP-21363SBBC-ENG Datasheet - Page 27

• Manufacturer Part Number: ADSP-21363SBBC-ENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Table 23. 16-bit Memory Write Cycle
1
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t
H = t
F = 7 x t
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
ALEW
ADAS
ALERW
RWALE
WRH
ADAH
WW
ALEHZ
DWS
DWH
PCLK
1
1
1
PCLK
(if a hold cycle is specified, else H = 0)
(if FLASH_MODE is set else F = 0)
AD15-0
ALE Pulse Width
Address/Data 15–0 Setup Before ALE Deasserted
ALE Deasserted to Write Asserted
Write Deasserted to ALE Asserted
Delay Between WR Rising Edge to next WR Falling Edge
Address/Data 15–0 Hold After ALE Deasserted
WR Pulse Width
ALE Deasserted to Address/Data15–0 in High Z
Address/Data 15–0 Setup Before WR High
Address/Data 15–0 Hold After WR High
ALE
WR
RD
t
ALEW
t
ADAS
ADDRESS
Figure 20. Write Cycle For 16-Bit Memory Timing
VALID
Rev. PrA | Page 27 of 44 | September 2004
t
ADAH
t
ALERW
VALID DATA
t
DWS
t
WW
t
DWH
t
WRH
Min
2 × t
t
2 × t
H + 0.5
F + H + t
t
D – F – 2
t
D – F + t
H
VALID DATA
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
– 2.5
– 0.5
– 1.5
PCLK
t
PCLK
– 2
– 2
RWALE
– 4
– 2
Max
ADSP-21363
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns