ADSP-21363SBBC-ENG AD [Analog Devices], ADSP-21363SBBC-ENG Datasheet - Page 12

• Manufacturer Part Number: ADSP-21363SBBC-ENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21363
Table 3. Pin Descriptions (Continued)
1
2
3
4
Pin
CLKIN
XTAL
CLKCFG1–0
RSTOUT/CLKOUT O
RESET
TCK
TMS
TDI
TDO
TRST
EMU
V
V
A
A
GND
RD, WR, and ALE are three-stated (and not driven) only when RESET is active.
Output only is a three-state driver with its output path always enabled.
Three-state is a three-state driver with pullup disabled.
Input only is a three-state driver with both output path and pullup disabled.
DDINT
DDEXT
VDD
VSS
Type
I
O
I
I/A
I
I/S
(pu)
I/S
(pu)
O
I/A
(pu)
O (O/D)
(pu)
P
P
P
G
G
State During &
After Reset
Input only
Output only
Input only
Output only
Input only
Input only
Three-state with
pullup enabled
Three-state with
pullup enabled
Three-state
Three-state with
pullup enabled
Three-state with
pullup enabled
3
4
2
Rev. PrA | Page 12 of 44 | September 2004
Function
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21363 clock input.
It configures the ADSP-21363 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the ADSP-21363 to use the external clock source such as an
external clock oscillator. The core is clocked either by the PLL output or this clock input
depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or
operated below the specified frequency.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
Core/CLKIN Ratio Control. These pins set the start up clock frequency. See
for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
Local Clock Out/ Reset Out. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin.The functionality can be switched
between the PLL output clock and reset out by setting bit 12 of the PMCTREG register.
The default is reset out.
Processor Reset. Resets the ADSP-21363 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must be
asserted (low) at power-up.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21363.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ
internal pullup resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 kΩ internal pullup resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21363. TRST has a
22.5 kΩ internal pullup resistor.
Emulation Status. Must be connected to the ADSP-21363 Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a 22.5 kΩ
internal pullup resistor.
Core Power Supply. Nominally +1.2 V dc and supplies the processor’s core
(13 pins on the Mini-BGA package, 32 pins on the LQFP package).
I/O Power Supply. Nominally +3.3 V dc. (6 pins on the Mini-BGA package, 10 pins on
the LQFP package).
Analog Power Supply. Nominally +1.2 V dc and supplies the processor’s internal PLL
(clock generator). This pin has the same specifications as V
filtering circuitry is required.
Analog Power Supply Return.
Power Supply Return. (54 pins on the Mini-BGA package, 39 pins on the LQFP
package).
For more information, see Power Supplies on Page 7.
Preliminary Technical Data
DDINT
, except that added
Table 6