ADSP-21363SBBC-ENG AD [Analog Devices], ADSP-21363SBBC-ENG Datasheet - Page 33

• Manufacturer Part Number: ADSP-21363SBBC-ENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
SPI Interface—Master
The ADSP-21363 contains two SPI ports. The primary has dedi-
cated pins and the secondary is available through the DAI. The
timing provided in
Table 30. SPI Interface Protocol — Master Switching and Timing Specifications
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SPICLKM
SPICHM
SPICLM
DDSPIDM
HDSPIDM
SDSCIM
HDSM
SPITDM
CPHASE=1
CPHASE=0
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
FLAG3-0
SPICLK
(CP = 0)
SPICLK
(CP = 1)
MOSI
(INPUT)
MOSI
(INPUT)
MISO
MISO
Table 30
Data Input Valid to SPICLK edge (Data Input Set-up Time)
SPICLK Last Sampling Edge to Data Input Not Valid
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge
Last SPICLK edge to FLAG3–0IN high
Sequential Transfer Delay
t
S S P ID M
and
t
S D S C I M
Table 31
VALID
MSB
t
t
MSB
S P I C H M
S P I C L M
VALID
MSB
t
applies to both.
H S P I D M
t
t
D D S P I D M
t
S S P I D M
t
MSB
S P I C L M
Rev. PrA | Page 33 of 44 | September 2004
S P I C H M
t
D D S P I D M
Figure 25. SPI Master Timing
t
H S S P I D M
t
H D S P I D M
t
t
S S P ID M
HDSPIDM
t
VALID
S P I C L K M
LSB
LSB
VALID
LSB
2
4 × t
4 × t
Min
8
8 × t
4 × t
4 × t
2
4 × t
t
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
H D S M
LSB
– 2
– 2
– 1
– 1
t
H S P I D M
t
S P I TD M
Max
0
ADSP-21363
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns