ADSP-21363SBBC-ENG AD [Analog Devices], ADSP-21363SBBC-ENG Datasheet - Page 25

• Manufacturer Part Number: ADSP-21363SBBC-ENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Table 21. 16-bit Memory Read Cycle
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t
H = t
F = 7 x t
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
DRS
DRH
ALEW
ADAS
ALERW
RRH
RWALE
RDDRV
ADAH
ALEHZ
RW
PCLK
1
1
1
PCLK
(if a hold cycle is specified, else H = 0)
(if FLASH_MODE is set else F = 0)
Address/Data 15–0 Setup Before RD High
Address/Data 15–0 Hold After RD High
ALE Pulse Width
Address/Data 15–0 Setup Before ALE Deasserted
ALE Deasserted to Read Asserted
Delay Between RD Rising Edge to Next Falling Edge.
Read Deasserted to ALE Asserted
RD Address Drive After Read High
Address/Data 15–0 Hold After ALE Deasserted
ALE Deasserted to Address/Data15–0 in High Z
RD Pulse Width
AD15-0
ALE
WR
RD
t
Figure 18. Read Cycle For 16-Bit Memory Timing
t
ADAS
ALEW
VALID ADDRESS
Rev. PrA | Page 25 of 44 | September 2004
t
ADAH
t
ALEHZ
t
ALERW
t
t
DRS
VALID DATA
RW
t
DRH
t
t
RDDRV
RRH
Min
3.3
0
t
H + t
F + H + 0.5
t
t
D – 2
2 × t
2 × t
F + H + t
t
PCLK
PCLK
PCLK
RW ALE
PCLK
ADDRESS
PCLK
PCLK
PCLK
VALID
– 2.5
– 0.8
– 0.8
PCLK
– 2
– 2
– 1
– 1
Max
ADSP-21363
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns