ADSP-21363SBBC-ENG AD [Analog Devices], ADSP-21363SBBC-ENG Datasheet - Page 10

• Manufacturer Part Number: ADSP-21363SBBC-ENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21363
PIN FUNCTION DESCRIPTIONS
ADSP-21363 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS and TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for TRST). Tie or pull unused inputs to
V
Table 3. Pin Descriptions
Pin
AD15–0
RD
WR
ALE
FLAG3–0
DDEXT
or GND, except for the following:
Type
I/O/T
(pu)
O
(pu)
O
(pu)
O
(pd)
I/O/A
State During &
After Reset
Three-state with
pullup enabled
Three-state, driven
high
Three-state, driven
high
Three-state, driven
low
Three-state
1
1
1
Rev. PrA | Page 10 of 44 | September 2004
Function
Parallel Port Address/Data. The ADSP-21363 parallel port and its corresponding
DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pullup resistor. See
Data Modes on Page 13
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper
16 external address bits, A23–8; ALE is used in conjunction with an external latch to
retain the values of the A23–8.
For 16-bit mode: ALE is automatically asserted whenever a change occurs in the
address bits, A15–0; ALE is used in conjunction with an external latch to retain the
values of the A15–0. To use these pins as flags (FLAGS15–0) or PWMs (PWM15–0), 1)
set (=1) bit 20 of the SYSCTL register to disable the parallel port, 2) set (=1) bits 22–25
of the SYSCTL register to enable FLAGS in groups of four (bit 22 for FLAGS3–0, bit 23
for FLAGS7–4 etc.) or, set (=1) bits 26–29 of the SYSCTL register to enable PWMs in
groups of four (bit 26 for PWM0–3, bit 27 for PWM4–7, and so on). When used as an
input, the IDP Channel 0 can use these pins for parallel input data.
Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or
16-bit data from an external memory device. When AD15–0 are flags, this pin remains
deasserted. RD has a 22.5 kΩ internal pullup resistor.
Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or
16-bit data to an external memory device. When AD15–0 are flags, this pin remains
deasserted. WR has a 22.5 kΩ internal pullup resistor.
Parallel Port Address Latch enable. ALE is asserted whenever the processor drives
a new address on the parallel port address pins. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD15–0 are flags, this
pin remains deasserted. ALE has a 20 kΩ internal pulldown resistor.
Flag Pins. Each flag pin is configured via control bits as either an input or output. As
an input, it can be tested as a condition. As an output, it can be used to signal external
peripherals. These pins can be used as an SPI interface slave select output during SPI
mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals.
In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an
SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When bit 16
is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.
When bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.
When bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.
When bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP which
indicates that the system timer has expired.
The following symbols appear in the Type column of
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State , (pd) = pulldown
resistor, (pu) = pullup resistor.
• DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI,
for details of the AD pin operation.
and AD15–0 (NOTE: These pins have pullup resistors.)
Preliminary Technical Data
Table
Address
3: