ADSP-21363SBBC-ENG AD [Analog Devices], ADSP-21363SBBC-ENG Datasheet - Page 34

• Manufacturer Part Number: ADSP-21363SBBC-ENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21363
SPI Interface—Slave
Table 31. SPI Interface Protocol —Slave Switching and Timing Specifications
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
SPICLKS
SPICHS
SPICLS
SDSCO
HDS
SSPIDS
HSPIDS
SDPPW
DSOE
DSDHI
DDSPIDS
HDSPIDS
DSOV
CPHASE=1
CPHASE=0
(OUTPUT)
(OUTPUT)
SPICLK
(CP = 0)
(INPUT)
SPICLK
(CP = 1)
(INPUT)
MISO
(INPUT)
MISO
(INPUT)
(INPUT)
SPIDS
MOSI
MOSI
t
S D S C O
t
t
t
D S O E
D S O E
D S O V
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
Data Input Valid to SPICLK edge (Data Input Set-up Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE=0)
SPIDS Assertion to Data Out Active
SPIDS Deassertion to Data High Impedance
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE=0)
t
t
S P IC H S
S S P I D S
t
t
D D S P I D S
MSB VALID
S P I C L S
MSB VALID
MSB
MSB
t
D D S P I D S
Rev. PrA | Page 34 of 44 | September 2004
t
t
S P I C H S
S P I C L S
Figure 26. SPI Slave Timing
t
S S P I D S
t
D D S P I D S
LSB VALID
t
t
S P I C L K S
S S P I D S
t
LSB
H D L S B S
LSB VALID
t
H S P I D S
Min
4 × t
2 × t
2 × t
2 × t
2 × t
2 × t
2
2
2 × t
0
0
2 × t
t
H S P I D S
t
H D S
LSB
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
Preliminary Technical Data
– 2
t
S D P P W
t
t
t
D S D H I
D S D H I
H D LS B S
Max
4
9.4
5 × t
4
PCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns