ADSP-21363SBBC-ENG AD [Analog Devices], ADSP-21363SBBC-ENG Datasheet - Page 7

• Manufacturer Part Number: ADSP-21363SBBC-ENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Each of the serial ports supports the left-justified sample pair
and I
monly used by audio codecs, ADCs and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I
devices) per serial port, with a maximum of up to 24 I
nels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I
word lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional µ-law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be inter-
nally or externally generated.
Parallel Port
The Parallel Port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15–0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16-
bit, the maximum data transfer rate is 55M bytes/sec.
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral-
lel port register read/write functions. The RD, WR, and ALE
(Address Latch Enable) pins are the control pins for the parallel
port.
Serial Peripheral (Compatible) Interface
The ADSP-21363 SHARC processor contains two Serial Periph-
eral Interface ports (SPIs). The SPI is an industry standard
synchronous serial link, enabling the ADSP-21363 SPI compati-
ble port to communicate with other SPI compatible devices. The
SPI consists of two data pins, one device select pin, and one
clock pin. It is a full-duplex synchronous serial interface, sup-
porting both master and slave modes. The SPI port can operate
in a multimaster environment by interfacing with up to four
other SPI compatible devices, either acting as a master or slave
device. The ADSP-21363 SPI compatible peripheral implemen-
tation also features programmable baud rate and clock phase
and polarities. The ADSP-21363 SPI compatible port uses open
drain drivers to support a multimaster configuration and to
avoid data contention.
Pulse Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave-
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non
paired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
each. Therefore this module generates 16 PWM outputs in total.
Each PWM group produces two pairs of PWM signals on the
four PWM outputs.
2
S protocols (I
2
S is an industry standard interface com-
2
S channels (using two stereo
2
S modes, data-
Rev. PrA | Page 7 of 44 | September 2004
2
S chan-
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode, or double update mode. In single update mode
the duty cycle values are programmable only once per PWM
period. This results in PWM patterns that are symmetrical
around the mid-point of the PWM period. In double update
mode, a second updating of the PWM registers is implemented
at the mid-point of the PWM period. In this mode, it is possible
to produce asymmetrical PWM patterns that produce lower
harmonic distortion in three-phase PWM inverters.
Timers
The ADSP-21363 has a total of four timers: a core timer able to
generate periodic software interrupts and three general purpose
timers that can generate periodic interrupts and be indepen-
dently set to operate in one of three modes:
The core timer can be configured to use FLAG3 as a Timer
Expired signal, and each general-purpose timer has one bidirec-
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables all three
general purpose timers independently.
Program Booting
The internal memory of the ADSP-21363 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1–0) pins. Selection of
the boot source is controlled via the SPI as either a master or
slave device.
Phase-Locked Loop
The ADSP-21363 uses an on-chip Phase-Locked Loop (PLL) to
generate the internal clock for the core. On power up, the
CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1.
After booting, numerous other ratios can be selected via soft-
ware control. The ratios are made up of software configurable
numerator values from 1 to 32 and software configurable divi-
sor values of 1, 2, 4, 8, and 16.
Power Supplies
The ADSP-21363 has separate power supply connections for the
internal (V
power supplies. The internal and analog supplies must meet the
1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.
Note that the analog supply (A
clock generator PLL. To produce a stable clock, programs
should provide an external circuit to filter the power input to
the A
an example circuit, see
• Pulse Waveform Generation mode
• Pulse Width Count /Capture mode
• External Event Watchdog mode
VDD
pin. Place the filter as close as possible to the pin. For
DDINT
), external (V
Figure
DDEXT
4. To prevent noise coupling, use
VDD
) powers the ADSP-21363’s
), and analog (A
ADSP-21363
VDD
/A
VSS
)