ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 189
ATA6602-PLQW
Manufacturer Part Number
ATA6602-PLQW
Description
Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATA6602-PLQW.pdf
(362 pages)
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4.16.2
4921C–AUTO–01/07
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
4-67
nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
Table 4-67
Table 4-70.
Figure 4-67. SPI Transfer Format with CPHA = 0
Figure 4-68. SPI Transfer Format with CPHA = 1
and
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
MSB first (DORD = 0)
LSB first (DORD = 1)
Figure
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
and
MSB first (DORD = 0)
LSB first (DORD = 1)
CPOL Functionality
Table
4-68. Data bits are shifted out and latched in on opposite edges of the SCK sig-
4-68, as done below.
MSB
LSB
MSB
LSB
Sample (Falling)
Sample (Rising)
Leading Edge
Setup (Falling)
Setup (Rising)
Bit 6
Bit 1
Bit 6
Bit 1
Bit 5
Bit 2
Bit 5
Bit 2
Bit 4
Bit 3
Bit 4
Bit 3
Bit 3
Bit 4
Sample (Falling)
Sample (Rising)
Setup (Falling)
Trailing eDge
Setup (Rising)
ATA6602/ATA6603
Bit 3
Bit 4
Bit 2
Bit 5
Bit 2
Bit 5
Bit 1
Bit 6
Bit 1
Bit 6
LSB
MSB
LSB
MSB
SPI Mode
0
1
2
3
Figure
189
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