ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 221
ATA6602-PLQW
Manufacturer Part Number
ATA6602-PLQW
Description
Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATA6602-PLQW.pdf
(362 pages)
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4.18.5
4921C–AUTO–01/07
Data Transfer
Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in
the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation
of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling
the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
When the receiver is enabled, the normal pin operation of the RxDn pin is overridden and given
the function as the Receiver's serial input. The XCKn will in both cases be used as the transfer
clock.
After initialization the USART is ready for doing data transfers. A data transfer is initiated by writ-
ing to the UDRn I/O location. This is the case for both sending and receiving data since the
transmitter controls the transfer clock. The data written to UDRn is moved from the transmit
buffer to the shift register when the shift register is ready to send a new frame.
Note:
The following code examples show a simple USART in MSPIM mode transfer function based on
polling of the Data Register Empty (UDREn) Flag and the Receive Complete (RXCn) Flag. The
USART has to be initialized before the function can be used. For the assembly code, the data to
be sent is assumed to be stored in Register R16 and the data received will be available in the
same register (R16) after the function returns.
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,
before loading it with new data to be transmitted. The function then waits for data to be present
in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the
value.
To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must
be read once for each byte transmitted. The input buffer operation is identical to normal USART
mode, i.e. if an overflow occurs the character last received will be lost, not the first data in the
buffer. This means that if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and the
UDRn is not read before all transfers are completed, then byte 3 to be received will be lost, and not
byte 1.
ATA6602/ATA6603
221
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