ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 58

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4.6.11.1
58
ATA6602/ATA6603
Clock Prescale Register – CLKPR
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
Read/Write
Initial Value
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLK-
PCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are writ-
ten. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out
period, nor clear the CLKPCE bit.
These bits define the division factor between the selected clock source and the internal sys-
tem clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The division
factors are given in
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro-
grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are
reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the
selected clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. Note that any value can be written to the CLKPS bits
regardless of the CKDIV8 Fuse setting. The Application software must ensure that a suffi-
cient division factor is chosen if the selected clock source has a higher frequency than the
maximum frequency of the device at the present operating conditions. The device is shipped
with the CKDIV8 Fuse programmed.
Bit
CLKPR to zero.
CLKPCE
R/W
7
0
Table 4-17 on page
R
6
–
0
R
5
–
0
59.
R
4
–
0
CLKPS3 CLKPS2 CLKPS1 CLKPS0
R/W
3
See Bit Description
R/W
2
R/W
1
R/W
0
4921C–AUTO–01/07
CLKPR